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M34C02
Sequential Read
This operation can be used after a Current Ad-
dress Read or a Random Address Read. The bus
master does acknowledge the data byte output,
and sends additional clock pulses so that the de-
vice continues to output the next byte in sequence.
To terminate the stream of bytes, the bus master
must not acknowledge the last byte, and must
generate a Stop condition, as shown in Figure 11..
The output data comes from consecutive address-
es, with the internal address counter automatically
incremented after each byte output. After the last
memory address, the address counter ‘rolls-over’,
and the device continues to output data from
memory address 00h.
Acknowledge in Read Mode
For all Read commands, the device waits, after
each byte read, for an acknowledgment during the
9
th
bit time. If the bus master does not drive Serial
Data (SDA) Low during this time, the device termi-
nates the data transfer and switches to its Stand-
by mode.
USE WITHIN A DRAM DIMM
In the application, the M34C02 is soldered directly
in the printed circuit module. The 3 Chip Enable in-
puts (pins 1, 2 and 3) are wired at V
CC
or V
SS
through the DIMM socket (see Table 5.). The pull-
up resistors needed for normal behavior of the I
2
C
bus are connected on the I
2
C bus of the mother-
board (as shown in Figure 12.).
The Write Control (WC
) of the M34C02 can be left
unconnected. However, connecting it to V
SS
is
recommended, to maintain full read and write ac-
cess.
Programming the M34C02
When the M34C02 is delivered, full read and write
access is given to the whole memory array. It is
recommended that the first step is to use the test
equipment to write the module information (such
as its access speed, its size, its organization) to
the first half of the memory, starting from the first
memory location. When the data has been validat-
ed, the test equipment can send a Write command
to the Protection Register, using the device select
code ’01100000b’ followed by an address and
data byte (made up of Don’t Care values) as
shown in Figure 7.. The first 128 bytes of the mem-
ory area are then write-protected, and the M34C02
will no longer respond to the specific device select
code ’0110000xb’. It is not possible to reverse this
sequence.
Table 5. DRAM DIMM Connections
INITIAL DELIVERY STATE
The device is delivered with the memory array
erased: all bits are set to 1 (each byte contains
FFh).
DIMM Position E2 E1 E0
0
V
SS
V
SS
V
SS
1
V
SS
V
SS
V
CC
2
V
SS
V
CC
V
SS
3
V
SS
V
CC
V
CC
4
V
CC
V
SS
V
SS
5
V
CC
V
SS
V
CC
6
V
CC
V
CC
V
SS
7
V
CC
V
CC
V
CC
