M34C02
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Table 17. AC Characteristics (M34C02-W, M34C02-L, M34C02-R)
Note: 1. For a reSTART condition, or following a Write cycle.
2. Sampled only, not 100% tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
Table 18. AC Characteristics (M34C02-F)
Note: 1. For a reSTART condition, or following a Write cycle.
2. Sampled only, not 100% tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
Test conditions specified in Table 11. and Table 7. or Table 8.
Symbol Alt. Parameter Min. Max. Unit
f
C
f
SCL
Clock Frequency 400 kHz
t
CHCL
t
HIGH
Clock Pulse Width High 600 ns
t
CLCH
t
LOW
Clock Pulse Width Low 1300 ns
t
DL1DL2
2
t
F
SDA Fall Time 20 300 ns
t
DXCX
t
SU:DAT
Data In Set Up Time 100 ns
t
CLDX
t
HD:DAT
Data In Hold Time 0 ns
t
CLQX
t
DH
Data Out Hold Time 200 ns
t
CLQV
3
t
AA
Clock Low to Next Data Valid (Access Time) 200 900 ns
t
CHDX
1
t
SU:STA
Start Condition Set Up Time 600 ns
t
DLCL
t
HD:STA
Start Condition Hold Time 600 ns
t
CHDH
t
SU:STO
Stop Condition Set Up Time 600 ns
t
DHDL
t
BUF
Time between Stop Condition and Next Start Condition 1300 ns
t
W
t
WR
Write Time 10 ms
Test conditions specified in Table 11. and Table 9. or Table 10.
Symbol Alt. Parameter Min. Max. Unit
f
C
f
SCL
Clock Frequency 100 kHz
t
CHCL
t
HIGH
Clock Pulse Width High 4000 ns
t
CLCH
t
LOW
Clock Pulse Width Low 4700 ns
t
DL1DL2
2
t
F
SDA Fall Time 20 300 ns
t
DXCX
t
SU:DAT
Data In Set Up Time 250 ns
t
CLDX
t
HD:DAT
Data In Hold Time 0 ns
t
CLQX
t
DH
Data Out Hold Time 200 ns
t
CLQV
3
t
AA
Clock Low to Next Data Valid (Access Time) 200 3500 ns
t
CHDX
1
t
SU:STA
Start Condition Set Up Time 4700 ns
t
DLCL
t
HD:STA
Start Condition Hold Time 4000 ns
t
CHDH
t
SU:STO
Stop Condition Set Up Time 4000 ns
t
DHDL
t
BUF
Time between Stop Condition and Next Start Condition 4700 ns
t
W
t
WR
Write Time 10 ms
