74HC_HCT259_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 30 July 2012 9 of 20
NXP Semiconductors
74HC259-Q100; 74HCT259-Q100
8-bit addressable latch
t
su
set-up time D, An to LE;
see Figure 10 and
Figure 11
V
CC
= 2.0 V 80 19 - 100 - 120 - ns
V
CC
= 4.5 V 16 7 - 20 - 24 - ns
V
CC
= 6.0 V 14 6 - 17 - 20 - ns
t
h
hold time D to LE; see Figure 10
and Figure 11
V
CC
= 2.0 V 0 19 - 0 - 0 - ns
V
CC
= 4.5 V 0 6- 0 - 0 -ns
V
CC
= 6.0 V 0 5- 0 - 0 -ns
An to LE
; see Figure 10
and Figure 11
V
CC
= 2.0 V 2 11 - 2 - 2 - ns
V
CC
= 4.5 V 2 4- 2 - 2 -ns
V
CC
= 6.0 V 2 3- 2 - 2 -ns
C
PD
power
dissipation
capacitance
f
i
= 1 MHz;
V
I
=GNDtoV
CC
[4]
-19- - - - -pF
74HCT259-Q100
t
pd
propagation
delay
D to Qn; see Figure 6
[2]
V
CC
= 4.5 V - 23 39 - 49 - 59 ns
V
CC
= 5.0 V; C
L
=15pF - 20 - - - - - ns
An to Qn; see Figure 7
[2]
V
CC
= 4.5 V - 25 41 51 62 ns
V
CC
= 5.0 V; C
L
=15pF - 20 - - - - - ns
LE
to Qn; see Figure 8
[2]
V
CC
= 4.5 V - 22 38 - 48 - 57 ns
V
CC
= 5.0 V; C
L
=15pF - 20 - - - - - ns
t
PHL
HIGH to LOW
propagation
delay
MR to Qn; see Figure 9
V
CC
= 4.5 V - 23 39 - 49 - 59 ns
V
CC
= 5.0 V; C
L
=15pF - 20 - - - - - ns
t
t
transition time see Figure 8
[3]
V
CC
= 4.5 V - 7 15 - 19 - 22 ns
t
W
pulse width LE HIGH or LOW;
see Figure 8
V
CC
= 4.5 V 19 11 - 24 - 29 - ns
MR
LOW; see Figure 9
V
CC
= 4.5 V 18 10 - 23 - 27 - ns
Table 8. Dynamic characteristics
…continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 12.
Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit
Min Typ
[1]
Max Min Max Min Max
