74HC_HCT259_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 30 July 2012 4 of 20
NXP Semiconductors
74HC259-Q100; 74HCT259-Q100
8-bit addressable latch
5.2 Pin description
6. Functional description
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
d = HIGH or LOW data one set-up time prior to the LOW-to-HIGH LE
transition;
q = lower case letter indicates the state of the referenced input one set-up time prior to the LOW-to-HIGH transition.
Table 2. Pin description
Symbol Pin Description
A0, A1, A2 1, 2, 3 address input
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 4, 5, 6, 7, 9, 10, 11, 12 latch output
GND 8 ground (0 V)
D 13 data input
LE
14 latch enable input (active LOW)
MR
15 conditional reset input (active LOW)
V
CC
16 supply voltage
Table 3. Function table
[1]
Operating mode Input Output
MR LE D A0 A1 A2 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
Reset (clear) LHXXXXLLLLLLLL
Demultiplexer
(active HIGH 8-channel)
decoder (when D = H)
LLdLLLQ=dLLLLLLL
LLdHLLLQ=dLLLLLL
LLdLHLLLQ=dLLLLL
LLdHHLLLLQ=dLLLL
LLdLLHLLLLQ=dLLL
LLdHLHLLLLLQ=dLL
LLdLHHLLLLLLQ=dL
LLdHHHLLLLLLLQ=d
Memory (no action) H H X X X X q
0
q
1
q
2
q
3
q
4
q
5
q
6
q
7
Addressable latch H L d L L L Q = d q
1
q
2
q
3
q
4
q
5
q
6
q
7
HLdHLLq
0
Q=d q
2
q
3
q
4
q
5
q
6
q
7
HLdLHLq
0
q
1
Q=d q
3
q
4
q
5
q
6
q
7
HLdHHLq
0
q
1
q
2
Q=d q
4
q
5
q
6
q
7
HLdLLHq
0
q
1
q
2
q
3
Q=d q
5
q
6
q
7
HLdHLHq
0
q
1
q
2
q
3
q
4
Q=d q
6
q
7
HLdLHHq
0
q
1
q
2
q
3
q
4
q
5
Q=d q
7
HLdHHHq
0
q
1
q
2
q
3
q
4
q
5
q
6
Q=d
