74HC_HCT259_Q100 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 1 — 30 July 2012 12 of 20
NXP Semiconductors
74HC259-Q100; 74HCT259-Q100
8-bit addressable latch
Measurement points are given in Table 9.
The shaded areas indicate when the input is permitted to change for predictable output performance.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 10. Data input to latch enable input set-up and hold times
001aah125
GND
GND
t
h
t
su
t
h
t
su
V
M
V
M
V
M
V
CC
V
OH
V
OL
V
CC
Qn output Q = D Q = D
LE input
D input
Measurement points are given in Table 9.
The shaded areas indicate when the input is permitted to change for predictable output performance.
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 11. Address input to latch enable input set-up and hold times
001aah126
V
M
ADDRESS STABLE
V
M
t
h
t
su
V
CC
GND
V
CC
GND
LE input
An input
Table 9. Measurement points
Type Input Output
V
M
V
M
V
X
V
Y
74HC259-Q100 0.5V
CC
0.5V
CC
0.1V
CC
0.9V
CC
74HCT259-Q100 1.3 V 1.3 V 0.1V
CC
0.9V
CC
