83905AMLF Datasheet 83905AMLF, 83905AGLF, 83905AGLFT | P13-P15

83905 Datasheet

VFQFN EPAD Thermal Release Path

In order to maximize both the removal of heat from the package

and the electrical performance, a land pattern must be

incorporated on the Printed Circuit Board (PCB) within the footprint

of the package corresponding to the exposed metal pad or

exposed heat slug on the package, as shown in Figure 4. The

solderable area on the PCB, as defined by the solder mask, should

be at least the same size/shape as the exposed pad/slug area on

the package to maximize the thermal/electrical performance.

Sufficient clearance should be designed on the PCB between the

outer edges of the land pattern and the inner edges of pad pattern

for the leads to avoid any shorts.

While the land pattern on the PCB provides a means of heat

transfer and electrical grounding from the package to the board

through a solder joint, thermal vias are necessary to effectively

conduct from the surface of the PCB to the ground plane(s). The

land pattern must be connected to ground through these vias. The

vias act as “heat pipes”. The number of vias (i.e. “heat pipes”) are

application specific and dependent upon the package power

dissipation as well as electrical conductivity requirements. Thus,

thermal and electrical analysis and/or testing are recommended to

determine the minimum number needed. Maximum thermal and

electrical performance is achieved when an array of vias is

incorporated in the land pattern. It is recommended to use as many

vias connected to ground as possible. It is also recommended that

the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz

copper via barrel plating. This is desirable to avoid any solder

wicking inside the via during the soldering process which may

result in voids in solder between the exposed pad/slug and the

thermal land. Precautions should be taken to eliminate any solder

voids between the exposed heat slug and the land pattern. Note:

These recommendations are to be used as a guideline only. For

further information, please refer to the Application Note on the

Surface Mount Assembly of Amkor’s Thermally/Electrically

Enhance Leadframe Base Package, Amkor Technology.

Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)

Recommendations for Unused Input and Output Pins

Inputs:

LVCMOS Control Pins

All control pins have internal pull-ups or pull-downs; additional

resistance is not required but can be added for additional

protection. A 1k resistor can be used.

Outputs:

LVCMOS Outputs

All unused LVCMOS output can be left floating. There should be no

trace attached.

SOLDERSOLDER

PINPIN EXPOSED HEAT SLUG

PIN PAD PIN PADGROUND PLANE LAND PATTERN

(GROUND PAD)

THERMAL VIA

83905 Datasheet

Layout Guideline

Figure 5 shows an example of 83905 application schematic. The

schematic example focuses on functional connections and is not

configuration specific. In this example, the device is operated at

= 3.3V and V

DDO

= 1.8V. The crystal inputs are loaded with an

18pf load resonant quartz crystal. The tuning capacitors (C1, C2)

are fairly accurate, but minor adjustments might be required. Refer

to the pin description and functional tables in the datasheet to

ensure the logic control inputs are properly set. For the LVCMOS

output drivers, two termination examples are shown in the

schematic. For additional termination examples are shown in the

LVCMOS Termination Application Note.

As with any high speed analog circuitry, the power supply pins are

vulnerable to random noise. To achieve optimum jitter

performance, power supply isolation is required. The 83905

provides separate V

and V

DDO

power supplies to isolate any

high switching noise from coupling into the internal oscillator. In

order to achieve the best possible filtering, it is highly

recommended that the 0.1uF capacitors on the device side of the

ferrite beads be placed on the device side of the PCB as close to

the power pins as possible. This is represented by the placement

of these capacitors in the schematic. If space is limited, the ferrite

beads, 10uF and 0.1uF capacitor connected to the board supplies

can be placed on the opposite side of the PCB. If space permits,

place all filter components on the device side of the board.

Power supply filter recommendations are a general guideline to be

used for reducing external noise from coupling into the devices.

The filter performance is designed for a wide range of noise

frequencies. This low-pass filter starts to attenuate noise at

approximately 0kHz. If a specific frequency noise component is

known, such as switching power supplies frequencies, it is

recommended that component values be adjusted and if required,

additional filtering be added. Additionally, good general design

practices for power plane voltage stability suggests adding bulk

capacitance in the local area of all devices.

Figure 5. Schematic of Recommended Layout

83905 Datasheet

Power Considerations

This section provides information on power dissipation and junction temperature for the 83905.

Equations and example calculations are also provided.

1. Power Dissipation.

The total power dissipation for the 83905 is the sum of the core power plus the analog power plus the power dissipated due to the load.

The following is the power dissipation for V

= 3.3V + 5% = 3.465V, which gives worst case results.

• Power (core)

MAX

= V

DD_MAX

* (I

+ I

DDO

) = 3.465V *(10mA + 5mA) = 51.9mW

• Output Impedance R

OUT

Power Dissipation due to Loading 50 to V

Output Current I

OUT

= V

DD_MAX

/ [2 * (50 + R

OUT

)] = 3.465V / [2 * (50 + 7)] = 30.4mA

• Power Dissipation on the R

OUT

per LVCMOS output

Power (R

OUT

) = R

OUT

* (I

OUT

)

= 7 * (30.4mA)

= 6.5mW per output

• Total Power Dissipation on the R

OUT

Total Power (R

OUT

) = 6.5mW * 6 = 39mW

Dynamic Power Dissipation at 25MHz

Power (25MHz) = C

* Frequency * (V

)

= 19pF * 25MHz * (3.465V)

= 5.70mW per output

Total Power (25MHz) = 5.70mW * 6 = 34.2mW

Total Power Dissipation

• Total Power

= Power (core)

MAX

+ Total Power (R

OUT

) + Total Power (25MHz)

= 51.98mW + 39mW + 34.2mW

= 125.1mW

2. Junction Temperature.

Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.

The maximum recommended junction temperature is 125°C.

The equation for Tj is as follows: Tj = 

* Pd_total + T

Tj = Junction Temperature



= Junction-to-Ambient Thermal Resistance

Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)

= Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance 

must be used. Assuming no air flow

and a multi-layer board, the appropriate value is 100.3°C/W per Table 7 below.

Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:

70°C + 0.125W *100.3°C/W = 82.5°C. This is below the limit of 125°C.

This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the

type of board (multi-layer).

Table 7. Thermal Resistance 

for 16-Lead TSSOP, Forced Convection



by Velocity

Meters per Second 012.5

Multi-Layer PCB, JEDEC Standard Test Boards 100.3°C/W 96.0°C/W 93.9°C/W

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21

83905AMLF

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Clock Buffer Low Skew 1:5 Fanout Buffer

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83905AMLF

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