LT3755/LT3755-1/LT3755-2
14
37551fd
applicaTions inForMaTion
when operating at high ambient temperatures. The ma-
jority of the power dissipation in the IC comes from the
supply current needed to drive the gate capacitance of
the external power MOSFET. This gate drive current can
be calculated as:
I
GATE
= f
SW
• Q
G
A low Q
G
power MOSFET should always be used when op-
erating at high input voltages, and the switching frequency
should also be chosen carefully to ensure that the IC does
not exceed a safe junction temperature. The internal junc-
tion temperature of the IC can be estimated by:
T
J
= T
A
+ [V
IN
(I
Q
+ f
SW
• Q
G
) • θ
JA
]
where T
A
is the ambient temperature, I
Q
is the quiescent
current of the part (maximum 1.7mA) and θ
JA
is the
package thermal impedance (68°C/W for the 3mm × 3mm
QFN package). For example, an application with T
A(MAX)
= 85°C, V
IN(MAX)
= 40V, f
SW
= 400kHz, and having a FET
with Q
G
= 20nC, the maximum IC junction temperature
will be approximately:
T
J
= 85°C + [40V (1.7mA + 400kHz • 20nC) • 68°C/W]
= 111°C
The Exposed Pad on the bottom of the package must be
soldered to a ground plane. This ground should then be
connected to an internal copper ground plane with thermal
vias placed directly under the package to spread out the
heat dissipated by the IC.
If LT3755 junction temperature reaches 165°C, the GATE
and PWMOUT pins will be driven to GND and the soft-
start (SS) pin will be discharged to GND. Switching will
be enabled after device temperature is reduced 10°C. This
function is intended to protect the device during momentary
thermal overload conditions.
Frequency Synchronization (LT3755-1 Only)
The LT3755-1 switching frequency can be synchronized to
an external clock using the SYNC pin. For proper operation,
the R
T
resistor should be chosen for a switching frequency
20% lower than the external clock frequency. The SYNC
pin is disabled during the soft-start period.
Observation of the following guidelines about the SYNC
waveform will ensure proper operation of this feature.
Driving SYNC with a 50% duty cycle waveform is always
a good choice, otherwise, maintain the duty cycle between
20% and 60%. When using both PWM and SYNC features,
the PWM signal rising edge should occur at least 200ns
before the SYNC rising edge (V
IH
) for optimal PWM
performance. If the SYNC pin is not used, it should be
connected to GND.
Open LED Detection (LT3755 and LT3755-2)
The LT3755 and LT3755-2 provide an open-drain status
pin, OPENLED, that pulls low when the FB pin is within
~50mV of its 1.25V regulated voltage. If the open LED
clamp voltage is programmed correctly using the FB pin,
then the FB pin should never exceed 1.1V when LEDs are
connected, therefore, the only way for the FB pin to be within
50mV of the regulation voltage is for an open LED event to
have occurred. The key difference between the LT3755 and
LT3755-2 is the behavior of the OPENLED pin when the FB
pin crosses and re-crosses the FB overvoltage threshold
(1.31V typ). The LT3755-2 asserts/de-asserts OPENLED
freely when crossing the 1.31V threshold. The LT3755,
by comparison, de-asserts OPENLED when FB exceeds
1.31V and is prevented from re-asserting OPENLED until
the FB pin falls below the 1.2V (typ) open LED threshold
and clears the fault. The LT3755-2 has the more general
purpose behavior and is recommended for applications
using OPENLED.
Input Capacitor Selection
The input capacitor supplies the transient input current for
the power inductor of the converter and must be placed
and sized according to the transient current requirements.
The switching frequency, output current and tolerable input
voltage ripple are key inputs to estimating the capacitor
value. An X7R type ceramic capacitor is usually the best
choice since it has the least variation with temperature and
DC bias. Typically, boost and SEPIC converters require a
lower value capacitor than a buck mode converter. As-
suming that a 100mV input voltage ripple is acceptable,
the required capacitor value for a boost converter can be
estimated as follows:
C
IN
(µF) = I
LED
(A) •
V
OUT
V
IN
• t
SW
(µs) •
µF
A • µs
