©2014 Integrated Device Technology, Inc.
JULY 2014
DSC 5687/3
1
Functional Block Diagram
HIGH-SPEED 2.5V
256/128K x 72
SYNCHRONOUS
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
IDT70T3719/99M
REPEAT
R
A
0
R
CNTEN
R
AD S
R
D
OUT
0-8_R
D
OUT
9-17_R
I/O
0R
-I/O
71R
D
IN
_R
ADDR_R
OE
R
7R
BE
0R
R/W
R
CE
0R
CE
1R
1
0
1/0
FT/PIPE
R
1a 0a1h 0h
ha
CLK
R
,
Counter/
Address
Reg.
ha
0/1
0h 1h
0a 1a
B
W
0
R
FT/PIPE
R
Counter/
Address
Reg.
CNTEN
L
ADS
L
REPEAT
L
D
OU T
18-26_R
D
OUT
27-35_R
B
W
0
L
B
W
7
L
I/O
0L
-I/O
71L
A
17L
(1)
A
0L
D
IN
_L
ADDR_L
OE
L
5687 drw 01
BE
7L
BE
0L
R/W
L
CE
0L
CE
1L
256/128K x 72
MEMORY
ARRAY
CLK
L
ah
FT/PIPE
L
0/1
1h 0h
1a 0a
B
W
7
R
,
JTAG
TCK
TRST
TMS
TDO
TDI
1
0
1/0
0h 1h0a 1a
ah
FT/PIPE
L
1/0
1/0
INTERRUPT
COLLISION
DETECTION
LOGIC
R/W
R
CE
0
R
CE
1
R
INT
L
COL
L
INT
R
COL
R
ZZ
CONTROL
LOGIC
ZZ
L
(2)
ZZ
R
(2)
A
17R
(1)
Byte 0
Byte 7
D
OUT
36-44_R
D
OUT
45-53_R
D
OUT
54-62_R
D
OUT
63-72_R
D
OUT
0-8_L
D
OUT
9-17_L
D
OUT
18-26_L
D
OUT
27-35_L
D
OUT
36-44_L
D
OUT
45-53_L
D
OUT
54-62_L
D
OUT
63-72_L
Byte 7
Byte 0
R/W
L
CE
0
L
CE
1
L
Features:
◆
True Dual-Port memory cells which allow simultaneous
access of the same memory location
◆
High-speed data access
– Commercial: 3.6ns (166MHz)/
4.2ns (133MHz)(max.)
– Industrial: 4.2ns (133MHz) (max.)
◆
Selectable Pipelined or Flow-Through output mode
◆
Counter enable and repeat features
◆
Dual chip enables allow for depth expansion without
additional logic
◆
Interrupt and Collision Detection Flags
◆
Full synchronous operation on both ports
– 6ns cycle time, 166MHz operation (23.9Gbps bandwidth)
– Fast 3.6ns clock to data out
– Self-timed write allows fast cycle time
1. Address A17 is a NC for the IDT70T3799.
2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and OPTx
and the sleep mode pins themselves (ZZx) are not affected during sleep mode.
NOTES:
– 1.7ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 166MHz
– Data input, address, byte enable and control registers
◆
Separate byte controls for multiplexed bus and bus
matching compatibility
◆
Dual Cycle Deselect (DCD) for Pipelined Output Mode
◆
2.5V (±100mV) power supply for core
◆
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on
each port
◆
Industrial temperature range (-40°C to +85°C) is
available at 133MHz
◆
Available in a 324-pin Green Ball Grid Array (BGA)
◆
Includes JTAG Functionality
◆
Green parts available, see ordering information
