6.42
IDT70T3719/99M
High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges
17
ADDRESS
An
t
CYC2
CLK
DATA
IN
R/
W
REPEAT
5687 drw 18
INTERNAL
(3)
ADDRESS
ADS
CNTEN
WRITE TO
ADS
ADDRESS
An
ADVANCE
COUNTER
WRITE TO
An+1
ADVANCE
COUNTER
WRITE TO
An+2
HOLD
COUNTER
WRITE TO
An+2
REPEAT
READ LAST
ADS
ADDRESS
An
DATA
OUT
t
SA
t
HA
,
An
,
t
SAD
t
HAD
t
SW
t
HW
t
SCN
t
HCN
t
SRPT
t
HRPT
t
SD
t
HD
t
CD1
An+1
An+2
An+2
An An+1 An+2
An+2
D
0
D
1
D
2
D
3
An An+1 An+2
An+2
ADVANCE
COUNTER
READ
An+1
ADVANCE
COUNTER
READ
An+2
HOLD
COUNTER
READ
An+2
(4)
Timing Waveform of Write with Address Counter Advance
(Flow-through or Pipelined Inputs)
(1)
Timing Waveform of Counter Repeat
(2,6)
ADDRESS
An
CLK
DATA
IN
Dn
Dn + 1
Dn + 1 Dn + 2
ADS
CNTEN
t
CH2
t
CL2
t
CYC2
5687 drw 17
INTERNAL
(3)
ADDRESS
An
(7)
An + 1
An + 2
An + 3
An + 4
Dn + 3
Dn + 4
t
SA
t
HA
t
SAD
t
HAD
WRITE
COUNTER HOLD
WRITE WITH COUNTER
WRITE
EXTERNAL
ADDRESS
WRITE
WITH COUNTER
t
SD
t
HD
t
SCN
t
HC
N
,
NOTES:
1. CE
0, BEn, and R/W = VIL; CE1 and REPEAT = VIH.
2.
CE
0, BEn = VIL; CE1 = VIH.
3. The "Internal Address" is equal to the "External Address" when ADS = V
IL and equals the counter output when ADS = VIH.
4. No dead cycle exists during REPEAT operation. A READ or WRITE cycle may be coincidental with the counter REPEAT cycle: Address loaded by last valid
ADS load will be accessed. For more information on REPEAT function refer to Truth Table II.
5. CNTEN = V
IL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is
written to during this cycle.
6. For Pipelined Mode user should add 1 cycle latency for outputs as per timing waveform of read cycle for pipelined operations.
