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70T3719MS166BBG

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
6.42
IDT70T3719/99M
High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges
22
Figure 4. Depth and Width Expansion with IDT70T3719/99M
NOTE:
1. A
18 is for IDT70T3719, A17 is for IDT70T3799.
5687 drw 23
IDT70T3719/99M
CE
0
CE
1
CE
1
CE
0
CE
0
CE
1
A
18
/A
17
(1)
CE
1
CE
0
V
DD
V
DD
IDT70T3719/99M
IDT70T3719/99M
IDT70T3719/99M
Control Inputs
Control Inputs
Control Inputs
Control Inputs
BE,
R/W,
OE,
CLK,
ADS,
REPEAT,
CNTEN
,
Depth and Width Expansion
The IDT70T3719/99M features dual chip enables (refer to Truth
Table I) in order to facilitate rapid and simple depth expansion with no
requirements for external logic. Figure 4 illustrates how to control the
various chip enables in order to expand two devices in depth.
The IDT70T3719/99M can also be used in applications requiring
expanded width, as indicated in Figure 4. Through combining the control
signals, the devices can be grouped as necessary to accommodate
applications needing 144-bits.
Register Sizes, and System Interface Parameter tables. Specifically,
commands for Array B must precede those for Array A in any JTAG
operations sent to the IDT70T3719/99M. Please reference Application
Note AN-411, "JTAG Testing of Multichip Modules" for specific instruc-
tions on performing JTAG testing on the IDT70T3719/99M. AN-411 is
available at www.idt.com.
Array A Array B
TCK
TMS
TRST
TDI TDOA TDIB
TDO
5687 drw 24
IDT70T3719/99M
Figure 5. JTAG Configuration for IDT70T3719/99M
JTAG Functionality and Configuration
.
The IDT70T3719/99M is composed of two independent memory
arrays, and thus cannot be treated as a single JTAG device in the scan
chain. The two arrays (A and B) each have identical characteristics and
commands but must be treated as separate entities in JTAG operations.
Please refer to Figure 5.
JTAG signaling must be provided serially to each array and utilize the
information provided in the Identification Register Definitions, Scan
6.42
IDT70T3719/99M
High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges
23
JTAG AC Electrical
Characteristics
(1,2,3,4)
70T3719/99M
Symbol Parameter Min. Max. Units
t
JCYC
JTAG Clock Input Period 100
____
ns
t
JCH
JTAG Clock HIGH 40
____
ns
t
JCL
JTAG Clock Low 40
____
ns
t
JR
JTAG Clock Rise Time
____
3
(1)
ns
t
JF
JTAG Clock Fall Time
____
3
(1)
ns
t
JRST
JTAG Reset 50
____
ns
t
JRSR
JTAG Reset Recovery 50
____
ns
t
JCD
JTAG Data Output
____
25 ns
t
JDC
JTAG Data Output Hold 0
____
ns
t
JS
JTAG Setup 15
____
ns
t
JH
JTAG Hold 15
____
ns
5687 tbl 16
NOTES:
1. Guaranteed by design.
2. 30pF loading on external output signals.
3. Refer to AC Electrical Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at
any speed specified in this datasheet.
JTAG Timing Specifications
TCK
Device Inputs
(1)
/
TDI/TMS
Device Outputs
(2)
/
TDO
TRST
t
JCD
t
JDC
t
JRST
t
JS
t
JH
t
JCYC
t
JRSR
t
JF
t
JCL
t
JR
t
JCH
5687 drw 25
,
Figure 5. Standard JTAG Timing
NOTES:
1. Device inputs = All device inputs except TDI, TMS, and TRST.
2. Device outputs = All device outputs except TDO.
6.42
IDT70T3719/99M
High-Speed 2.5V 256/128K x 72 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges
24
Identification Register Definitions
Instruction Field
Array
B
Value
Array
B
Instruction Field
Array
A
Value
Array
A
Description
Revision Number (31:28) 0x0 Revision Number (63:60) 0x0 Reserved for Version number
IDT Device ID (27:12)
(1)
0x330
IDT Device ID (59:44)
(1)
0x330 Defines IDT Part number
IDT JEDEC ID (11:1) 0x33 IDT JEDEC ID (43:33) 0x33 Allows unique identification of device vendor as IDT
ID Register Indicator Bit (Bit 0) 1 ID Register Indicator Bit (Bit 32) 1 Indicates the presence of an ID Register
5687 tbl 17
Scan Register Sizes
Register Name
Bit Size
Array A
Bit Size
Array B
Bit Size
70T3719M
Instruction (IR) 4 4 8
Bypass (BYR) 1 1 2
Identification (IDR) 32 32 64
Boundary Scan (BSR) Note (3) Note (3) Note (3)
5687 tbl 18
System Interface Parameters
Instruction Code Description
EXTEST 00000000 Forces contents of the boundary scan cells onto the device outputs
(1)
.
Places the boundary scan register (BSR) between TDI and TDO.
BYPASS 11111111 Places the bypass register (BYR) between TDI and TDO.
IDCODE 00100010 Loads the ID register (IDR) with the vendor ID code and places the
register between TDI and TDO.
HIGHZ
01000100 Places the bypass register (BYR) between TDI and TDO. Forces all
device output drivers except INTx and COLx to a High-Z state.
CLAMP 00110011
Uses BYR. Forces contents of the boundary scan cells onto the device
outputs. Places the bypass register (BYR) between TDI and TDO.
SAMPLE/PRELOAD 00010001 Places the boundary scan register (BSR) between TDI and TDO.
SAMPLE allows data from device inputs
(2)
to be captured in the
boundary scan cells and shifted serially through TDO. PRELOAD allows
data to be input serially into the boundary scan cells via the TDI.
RESERVED 01010101, 01110111,
10001000, 10011001,
10101010, 10111011,
11001100
Several combinations are reserved. Do not use codes other than those
identified above.
P RIVATE 01100110,11101110,
11011101
For internal use only.
5687 tbl 19
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, and TRST.
3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by contacting your local
IDT sales representative.
NOTE:
1. Device ID for IDT70T3719M is 0x330. Device ID for IDT70T3799M is 0x331.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25

70T3719MS166BBG

Mfr. #:
Buy 70T3719MS166BBG
Manufacturer:
IDT
Description:
SRAM 256K X 72 STD-PWR 2.5V DUAL PORT RAM
Lifecycle:
New from this manufacturer.
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