18
4428E–8051–02/08
AT/TS80C31X2
A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-prior-
ity interrupt. A high-priority interrupt can’t be interrupted by any other interrupt source.
If two interrupt requests of different priority levels are received simultaneously, the request of
higher priority level is serviced. If interrupt requests of the same priority level are received simul-
taneously, an internal polling sequence determines which request is serviced. Thus within each
priority level there is a second priority structure determined by the polling sequence.
Table 10-2. IE Register -- IE - Interrupt Enable Register (A8h)
Reset Value = 0XX0 0000b
Bit addressable
7 6 5 4 3 2 1 0
EA - - ES ET1 EX1 ET0 EX0
Bit
Number
Bit
Mnemonic Description
7 EA
Enable All interrupt bit
Clear to disable all interrupts.
Set to enable all interrupts.
If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its
own interrupt enable bit.
6 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4 ES
Serial port Enable bit
Clear to disable serial port interrupt.
Set to enable serial port interrupt.
3 ET1
Timer 1 overflow interrupt Enable bit
Clear to disable timer 1 overflow interrupt.
Set to enable timer 1 overflow interrupt.
2 EX1
External interrupt 1 Enable bit
Clear to disable external interrupt 1.
Set to enable external interrupt 1.
1 ET0
Timer 0 overflow interrupt Enable bit
Clear to disable timer 0 overflow interrupt.
Set to enable timer 0 overflow interrupt.
0 EX0
External interrupt 0 Enable bit
Clear to disable external interrupt 0.
Set to enable external interrupt 0.
