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AT80C31X2-RLTUM

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42
22
4428E–8051–02/08
AT/TS80C31X2
Figure 11-1. Power-Down Exit Waveform
Exit from power-down by reset redefines all the SFRs, exit from power-down by external inter-
rupt does no affect the SFRs.
Exit from power-down by either reset or external interrupt does not affect the internal RAM
content.
Note: NOTE: If idle mode is activated with power-down mode (IDL and PD bits set), the exit sequence is
unchanged, when execution is vectored to interrupt, PD and IDL bits are cleared and idle mode is
not entered.
Table 11-1. The state of ports during idle and power-down modes
Mode
Program
Memory ALE PSEN PORT0 PORT1 PORT2 PORT3
Idle External 1 1 Floating Port Data Address Port Data
Power Down External 0 0 Floating Port Data Port Data Port Data
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4428E–8051–02/08
AT/TS80C31X2
12. ONCE
TM
Mode (ON Chip Emulation)
The ONCE mode facilitates testing and debugging of systems using TS80C31X2 without remov-
ing the circuit from the board. The ONCE mode is invoked by driving certain pins of the
TS80C31X2; the following sequence must be exercised:
• Pull ALE low while the device is in reset (RST high) and PSEN is high.
• Hold ALE low as RST is deactivated.
While the TS80C31X2 is in ONCE mode, an emulator or test CPU can be used to drive the cir-
cuit Table 26. shows the status of the port pins during ONCE mode.
Normal operation is restored when normal reset is applied.
Table 12-1. External Pin Status during ONCE Mode
ALE PSEN Port 0 Port 1 Port 2 Port 3 XTAL1/2
Weak pull-up Weak pull-up Float Weak pull-up Weak pull-up Weak pull-up Active
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4428E–8051–02/08
AT/TS80C31X2
13. Power-Off Flag
The power-off flag allows the user to distinguish between a “cold start” reset and a “warm start”
reset.
A cold start reset is the one induced by V
CC
switch-on. A warm start reset occurs while V
CC
is still
applied to the device and could be generated for example by an exit from power-down.
The power-off flag (POF) is located in PCON register (See Table 13-1.). POF is set by hardware
when V
CC
rises from 0 to its nominal voltage. The POF can be set or cleared by software allow-
ing the user to determine the type of reset.
The POF value is only relevant with a Vcc range from 4.5V to 5.5V. For lower Vcc value, reading
POF bit will return indeterminate value.
Table 13-1. PCON Register -- PCON - Power Control Register (87h)
Reset Value = 00X1 0000b
Not bit addressable
7 6 5 4 3 2 1 0
SMOD1 SMOD0 - POF GF1 GF0 PD IDL
Bit
Number
Bit
Mnemonic Description
7 SMOD1
Serial port Mode bit 1
Set to select double baud rate in mode 1, 2 or 3.
6 SMOD0
Serial port Mode bit 0
Clear to select SM0 bit in SCON register.
Set to to select FE bit in SCON register.
5 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4 POF
Power-Off Flag
Clear to recognize next reset type.
Set by hardware when V
CC
rises from 0 to its nominal voltage. Can also be set by software.
3 GF1
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
2 GF0
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
1 PD
Power-Down mode bit
Cleared by hardware when reset occurs.
Set to enter power-down mode.
0 IDL
Idle mode bit
Clear by hardware when interrupt or reset occurs.
Set to enter idle mode.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42

AT80C31X2-RLTUM

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IC MCU 8BIT ROMLESS 44VQFP
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