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AT80C31X2-RLTUM

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42
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4428E–8051–02/08
AT/TS80C31X2
6. TS80C31X2 Enhanced Features
In comparison to the original 80C31, the TS80C31X2 implements some new features, which
are
:
• The X2 option.
• The Dual Data Pointer.
• The 4 level interrupt priority system.
• The power-off flag.
• The ONCE mode.
• Enhanced UART
6.1 X2 Feature
The TS80C31X2 core needs only 6 clock periods per machine cycle. This feature called ”X2”
provides the following advantages:
• Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.
• Save power consumption while keeping same CPU power (oscillator power saving).
• Save power consumption by dividing dynamically operating frequency by 2 in operating and
idle modes.
• Increase CPU power by 2 while keeping same crystal frequency.
In order to keep the original C51 compatibility, a divider by 2 is inserted between the XTAL1 sig-
nal and the main clock input of the core (phase generator). This divider may be disabled by
software.
6.1.1 Description
The clock for the whole circuit and peripheral is first divided by two before being used by the
CPU core and peripherals. This allows any cyclic ratio to be accepted on XTAL1 input. In X2
mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to
60%. Figure 6-1. shows the clock generation block diagram. X2 bit is validated on XTAL1÷2 ris-
ing edge to avoid glitches when switching from X2 to STD mode. Figure 6-2. shows the mode
switching waveforms.
Figure 6-1. Clock Generation Diagram
XTAL1
2
CKCON reg
X2
state machine: 6 clock cycles.
CPU control
F
OSC
F
XTAL
0
1
XTAL1:2
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4428E–8051–02/08
AT/TS80C31X2
Figure 6-2. Mode Switching Waveforms
The X2 bit in the CKCON register (See Table 6-1.) allows to switch from 12 clock cycles per
instruction to 6 clock cycles and vice versa. At reset, the standard speed is activated (STD
mode). Setting this bit activates the X2 feature (X2 mode).
CAUTION
In order to prevent any incorrect operation while operating in X2 mode, user must be aware that
all peripherals using clock frequency as time reference (UART, timers) will have their time refer-
ence divided by two. For example a free running timer generating an interrupt every 20 ms will
then generate an interrupt every 10 ms. UART with 4800 baud rate will have 9600 baud rate.
Reset Value = XXXX XXX0b
Not bit addressable
For further details on the X2 feature, please refer to ANM072 available on the web
(http://www.atmel-wm.com)
Table 6-1. CKCON Register
CKCON - Clock Control Register (8Fh)
7 6 5 4 3 2 1 0
- - - - - - - X2
Bit
Number
Bit
Mnemonic Description
7 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
1 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
0 X2
CPU and peripheral clock bit
Clear to select 12 clock periods per machine cycle (STD mode, F
OSC
=F
XTAL
/2).
Set to select 6 clock periods per machine cycle (X2 mode, F
OSC
=F
XTAL
).
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4428E–8051–02/08
AT/TS80C31X2
7. Dual Data Pointer Register Ddptr
The additional data pointer can be used to speed up code execution and reduce code size in a
number of ways.
The dual DPTR structure is a way by which the chip will specify the address of an external data
memory location. There are two 16-bit DPTR registers that address the external memory, and a
single bit called
DPS = AUXR1/bit0 (See Table 5.) that allows the program code to switch between them (Refer
to Figure 7-1).
Figure 7-1. Use of Dual Pointer
Reset Value = XXXX XXX0
Not bit addressable
Table 7-1. AUXR1: Auxiliary Register 1
7 6 5 4 3 2 1 0
- -3 - - - - - DPS
Bit
Number
Bit
Mnemonic Description
7 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
6 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
4 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
3 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
2 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
1 -
Reserved
The value read from this bit is indeterminate. Do not set this bit.
0 DPS
Data Pointer Selection
Clear to select DPTR0.
Set to select DPTR1.
External Data Memory
AUXR1(A2H)
DPS
DPH(83H) DPL(82H)
07
DPTR0
DPTR1
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AT80C31X2-RLTUM

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