AD9243ASZRL Datasheet AD9243ASZ, AD9243ASZRL | P10-P12

AD9243

REV. A

–9–

The input SHA of the AD9243 is optimized to meet the perfor-

mance requirements for some of the most demanding commu-

nication, imaging, and data acquisition applications while

maintaining low power dissipation. Figure 22 is a graph of the

full-power bandwidth of the AD9243, typically 40 MHz. Note

that the small signal bandwidth is the same as the full-power

bandwidth. The settling time response to a full-scale stepped

input is shown in Figure 23 and is typically 80 ns to 0.0025%.

The low input referred noise of 0.36 LSB’s rms is displayed via

a grounded histogram and is shown in Figure 13.

FREQUENCY – MHz

–3

–12

1 10010

AMPLITUDE – dB

–6

–9

Figure 22. Full-Power Bandwidth

SETTLING TIME – ns

CODE

16000

12000

06010 20 30 40 50

8000

4000

70 80

Figure 23. Settling Time

The SHA’s optimum distortion performance for a differential or

single-ended input is achieved under the following two condi-

tions: (1) the common-mode voltage is centered around mid

supply (i.e., AVDD/2 or approximately 2.5 V) and (2) the input

signal voltage span of the SHA is set at its lowest (i.e., 2 V input

span). This is due to the sampling switches, Q

, being CMOS

switches whose R

resistance is very low but has some signal

dependency which causes frequency dependent ac distortion

while the SHA is in the track mode. The R

resistance of a

CMOS switch is typically lowest at its midsupply but increases

symmetrically as the input signal approaches either AVDD or

AVSS. A lower input signal voltage span centered at midsupply

reduces the degree of R

modulation.

Figure 24 compares the AD9243’s THD vs. frequency perfor-

mance for a 2 V input span with a common-mode voltage of

1 V and 2.5 V. Note the difference in the amount of degrada-

tion in THD performance as the input frequency increases.

Similarly, note how the THD performance at lower frequencies

becomes less sensitive to the common-mode voltage. As the

input frequency approaches dc, the distortion will be domi-

nated by static nonlinearities such as INL and DNL. It is

important to note that these dc static nonlinearities are inde-

pendent of any R

modulation.

FREQUENCY – MHz

THD – dB

–50

–60

–90

0.1 1 10

–70

–80

= 1.0V

= 2.5V

Figure 24. AD9243 THD vs. Frequency for V

= 2.5 V and

1.0 V (A

= –0.5 dB, Input Span = 2.0 V p-p)

Due to the high degree of symmetry within the SHA topology, a

significant improvement in distortion performance for differen-

tial input signals with frequencies up to and beyond Nyquist can

be realized. This inherent symmetry provides excellent cancella-

tion of both common-mode distortion and noise. Also, the

required input signal voltage span is reduced by a half which

further reduces the degree of R

modulation and its effects on

distortion.

The optimum noise and dc linearity performance for either

differential or single-ended inputs is achieved with the largest

input signal voltage span (i.e., 5 V input span) and matched

input impedance for VINA and VINB. Note that only a slight

degradation in dc linearity performance exists between the

2 V and 5 V input span as specified in the AD9243 “DC

SPECIFICATIONS.”

Referring to Figure 21, the differential SHA is implemented

using a switched-capacitor topology. Hence, its input imped-

ance and its subsequent effects on the input drive source should

be understood to maximize the converter’s performance. The

combination of the pin capacitance, C

, parasitic capacitance

PAR,

and the sampling capacitance, C

, is typically less than

16 pF. When the SHA goes into track mode, the input source

must charge or discharge the voltage stored on C

to the new

input voltage. This action of charging and discharging C

which

is approximately 4 pF, averaged over a period of time and for a

given sampling frequency, F

, makes the input impedance ap-

pear to have a benign resistive component (i.e., 83 kΩ at F

3.0 MSPS). However, if this action is analyzed within a sam-

pling period (i.e., T = <1/F

), the input impedance is dynamic

due to the instantaneous requirement of charging and discharg-

ing C

. A series resistor inserted between the input drive source

and the SHA input as shown in Figure 25 provides the effective

isolation.

AD9243

REV. A

–10–

10mF

VINA

VINB

SENSE

AD9243

0.1mF

VREF

REFCOM

*OPTIONAL SERIES RESISTOR

Figure 25. Series Resistor Isolates Switched-Capacitor

SHA Input from Op Amp. Matching Resistors Improve

SNR Performance

The optimum size of this resistor is dependent on several factors

which include the AD9243 sampling rate, the selected op amp,

and the particular application. In most applications, a 30 Ω to

50 Ω resistor is sufficient. However, some applications may re-

quire a larger resistor value to reduce the noise bandwidth or

possibly limit the fault current in an overvoltage condition.

Other applications may require a larger resistor value as part of

an anti-aliasing filter. In any case, since the THD performance

is dependent on the series resistance and the above mentioned

factors, optimizing this resistor value for a given application is

encouraged.

A slight improvement in SNR performance and dc offset perfor-

mance is achieved by matching the input resistance connected

to VINA and VINB. The degree of improvement is dependent on

the resistor value and the sampling rate. For series resistor

values greater than 100 Ω, the use of a matching resistor is

encouraged.

The noise or small-signal bandwidth of the AD9243 is the same

as its full-power bandwidth. For noise sensitive applications, the

excessive bandwidth may be detrimental and the addition of a

series resistor and/or shunt capacitor can help limit the wide-

band noise at the A/D’s input by forming a low-pass filter.

Note, however, that the combination of this series resistance

with the equivalent input capacitance of the AD9243 should be

evaluated for those time-domain applications that are sensitive

to the input signal’s absolute settling time. In applications where

harmonic distortion is not a primary concern, the series resis-

tance may be selected in combination with the SHA’s nominal

16 pF of input capacitance to set the filter’s 3 dB cutoff frequency.

A better method of reducing the noise bandwidth, while possi-

bly establishing a real pole for an antialiasing filter, is to add

some additional shunt capacitance between the input (i.e.,

VINA and/or VINB) and analog ground. Since this additional

shunt capacitance combines with the equivalent input capaci-

tance of the AD9243, a lower series resistance can be selected to

establish the filter’s cutoff frequency while not degrading the

distortion performance of the device. The shunt capacitance

also acts like a charge reservoir, sinking or sourcing the addi-

tional charge required by the hold capacitor, C

, further reduc-

ing current transients seen at the op amp’s output.

The effect of this increased capacitive load on the op amp driv-

ing the AD9243 should be evaluated. To optimize performance

when noise is the primary consideration, increase the shunt

capacitance as much as the transient response of the input signal

will allow. Increasing the capacitance too much may adversely

affect the op amp’s settling time, frequency response, and dis-

tortion performance.

Table I. Analog Input Configuration Summary

Input Input Input Range (V) Figure

Connection Coupling Span (V) VINA

VINB

# Comments

Single-Ended DC 2 0 to 2 1 32, 33 Best for stepped input response applications, suboptimum

THD and noise performance, requires ±5 V op amp.

2 × VREF 0 to VREF 32, 33 Same as above but with improved noise performance due to

2 × VREF increase in dynamic range. Headroom/settling time require-

ments of ±5 op amp should be evaluated.

5 0 to 5 2.5 32, 33 Optimum noise performance, excellent THD performance. Requires

op amp with VCC > +5 V due to insufficient headroom @ 5 V.

2 × VREF 2.5 – VREF 2.5 39 Optimum THD performance with VREF = 1, noise performance

to improves while THD performance degrades as VREF increases

2.5 + VREF to 2.5 V. Single supply operation (i.e., +5 V) for many op amps.

Single-Ended AC 2 or 0 to 1 or 1 or VREF 34 Suboptimum ac performance due to input common-mode

2 × VREF 0 to 2 × VREF level not biased at optimum midsupply level (i.e., 2.5 V).

5 0 to 5 2.5 34 Optimum noise performance, excellent THD performance.

2 × VREF 2.5 – VREF 2.5 35 Flexible input range, Optimum THD performance with

to VREF = 1. Noise performance improves while THD perfor-

2.5 + VREF mance degrades as VREF increases to 2.5 V.

Differential AC or 2 2 to 3 3 to 2 29–31 Optimum full-scale THD and SFDR performance well be-

DC yond the A/Ds Nyquist frequency.

2 × VREF 2.5 – VREF/2 2.5 + VREF/2 29–31 Same as 2 V to 3 V input range with the exception that full-scale

to to THD and SFDR performance can be traded off for better noise

2.5 + VREF/2 2.5 – VREF/2 performance.

5 1.75 to 3.25 3.25 to 1.75 29–31 Widest dynamic range (i.e., ENOBs) due to Optimum Noise

performance.

NOTE

VINA and VINB can be interchanged if signal inversion is required.

AD9243

REV. A

–11–

REFERENCE OPERATION

The AD9243 contains an onboard bandgap reference that pro-

vides a pin-strappable option to generate either a 1 V or 2.5 V

output. With the addition of two external resistors, the user can

generate reference voltages other than 1 V and 2.5 V. Another

alternative is to use an external reference for designs requiring

enhanced accuracy and/or drift performance. See Table II for a

summary of the pin-strapping options for the AD9243 reference

configurations.

Figure 26 shows a simplified model of the internal voltage

reference of the AD9243. A pin-strappable reference amplifier

buffers a 1 V fixed reference. The output from the reference

amplifier, A1, appears on the VREF pin. The voltage on the

VREF pin determines the full-scale input span of the A/D. This

input span equals,

Full-Scale Input Span = 2

VREF

5kV

LOGIC

7.5kV

LOGIC

5kV

A/D

CAPT

VREF

DISABLE

REFCOM

SENSE

CAPB

AD9243

Figure 26. Equivalent Reference Circuit

The voltage appearing at the VREF pin as well as the state of

the internal reference amplifier, A1, are determined by the volt-

age appearing at the SENSE pin. The logic circuitry contains

two comparators which monitor the voltage at the SENSE pin.

The comparator with the lowest set point (approximately 0.3 V)

controls the position of the switch within the feedback path of

A1. If the SENSE pin is tied to REFCOM, the switch is con-

nected to the internal resistor network thus providing a VREF of

2.5 V. If the SENSE pin is tied to the VREF pin via a short or

resistor, the switch is connected to the SENSE pin. A short will

provide a VREF of 1.0 V while an external resistor network will

provide an alternative VREF between 1.0 V and 2.5 V. The

other comparator controls internal circuitry which will disable

the reference amplifier if the SENSE pin is tied AVDD. Dis-

abling the reference amplifier allows the VREF pin to be driven

by an external voltage reference.

The actual reference voltages used by the internal circuitry of

the AD9243 appear on the CAPT and CAPB pins. For proper

operation when using the internal or an external reference, it is

necessary to add a capacitor network to decouple these pins.

Figure 27 shows the recommended decoupling network. This

capacitive network performs the following three functions: (1)

along with the reference amplifier, A2, it provides a low source

impedance over a large frequency range to drive the A/D inter-

nal circuitry, (2) it provides the necessary compensation for A2,

and (3) it bandlimits the noise contribution from the reference.

The turn-on time of the reference voltage appearing between

CAPT and CAPB is approximately 15 ms and should be evalu-

ated in any power-down mode of operation.

0.1mF

10mF

0.1mF

CAPT

CAPB

AD9243

Figure 27. Recommended CAPT/CAPB Decoupling Network

The A/D’s input span may be varied dynamically by changing

the differential reference voltage appearing across CAPT and

CAPB symmetrically around 2.5 V (i.e., midsupply). To change

the reference at speeds beyond the capabilities of A2, it will be

necessary to drive CAPT and CAPB with two high speed, low

noise amplifiers. In this case, both internal amplifiers (i.e., A1

and A2) must be disabled by connecting SENSE to AVDD and

VREF to REFCOM and the capacitive decoupling network

removed. The external voltages applied to CAPT and CAPB

must be 2.5 V + Input Span/4 and 2.5 V – Input Span/4 respec-

tively in which the input span can be varied between 2 V and 5 V.

Note that those samples within the pipeline A/D during any

reference transition will be corrupted and should be discarded.

Table II. Reference Configuration Summary

Reference Input Span (VINA–VINB)

Operating Mode (V p-p) Required VREF (V) Connect To

INTERNAL 2 1 SENSE VREF

INTERNAL 5 2.5 SENSE REFCOM

INTERNAL 2 ≤ SPAN ≤ 5 AND 1 ≤ VREF ≤ 2.5 AND R1 VREF AND SENSE

SPAN = 2 × VREF VREF = (1 + R1/R2) R2 SENSE AND REFCOM

EXTERNAL 2 ≤ SPAN ≤ 51 ≤ VREF ≤ 2.5 SENSE AVDD

(NONDYNAMIC) VREF EXT. REF.

EXTERNAL 2 ≤ SPAN ≤ 5 CAPT and CAPB SENSE AVDD

(DYNAMIC) Externally Driven VREF REFCOM

EXT. REF. CAPT

EXT. REF. CAPB

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P25

AD9243ASZRL

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Analog to Digital Converters - ADC Complete 14B 3 MSPS Monolithic

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AD9243ASZRL

AD9243ASZRL

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