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AD9243ASZRL

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P25
AD9243
REV. A
–18–
until the analog input returns within the input range and an-
other conversion is completed. By logical ANDing OTR with
the MSB and its complement, overrange high or underrange low
conditions can be detected. Table V is a truth table for the over/
underrange circuit in Figure 43 which uses NAND gates. Sys-
tems requiring programmable gain conditioning of the AD9243
input signal can immediately detect an out-of-range condition,
thus eliminating gain selection iterations. Also, OTR can be
used for digital offset and gain calibration.
Table V. Out-of-Range Truth Table
OTR MSB Analog Input Is
0 0 In Range
0 1 In Range
1 0 Underrange
1 1 Overrange
OVER = “1”
UNDER = “1”
MSB
OTR
MSB
Figure 43. Overrange or Underrange Logic
Digital Output Driver Considerations (DRVDD)
The AD9243 output drivers can be configured to interface with
+5 V or 3.3 V logic families by setting DRVDD to +5 V or 3.3 V
respectively. The AD9243 output drivers are sized to provide
sufficient output current to drive a wide variety of logic families.
However, large drive currents tend to cause glitches on the
supplies and may affect SINAD performance. Applications requir-
ing the AD9243 to drive large capacitive loads or large fanout
may require additional decoupling capacitors on DRVDD. In
extreme cases, external buffers or latches may be required.
Clock Input and Considerations
The AD9243 internal timing uses the two edges of the clock
input to generate a variety of internal timing signals. The clock
input must meet or exceed the minimum specified pulsewidth
high and low (t
CH
and t
CL
) specifications for the given A/D as
defined in the Switching Specifications at the beginning of the
data sheet to meet the rated performance specifications. For
example, the clock input to the AD9243 operating at 3 MSPS
may have a duty cycle between 45% to 55% to meet this timing
requirement since the minimum specified t
CH
and t
CL
is 150 ns.
For clock rates below 3 MSPS, the duty cycle may deviate from
this range to the extent that both t
CH
and t
CL
are satisfied.
All high speed high resolution A/Ds are sensitive to the quality
of the clock input. The degradation in SNR at a given full-scale
input frequency (f
IN
) due to only aperture jitter (t
A
) can be
calculated with the following equation:
SNR = 20 log
10
[1/(2 π f
IN
t
A
)]
In the equation, the rms aperture jitter, t
A
, represents the root-
sum square of all the jitter sources which include the clock in-
put, analog input signal, and A/D aperture jitter specification.
For example, if a 1.5 MHz full-scale sine wave is sampled by an
A/D with a total rms jitter of 15 ps, the SNR performance of the
A/D will be limited to 77 dB. Undersampling applications are
particularly sensitive to jitter.
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the
AD9243. As such, supplies for clock drivers should be separated
from the A/D output driver supplies to avoid modulating the
clock signal with digital noise. Low jitter crystal controlled
oscillators make the best clock sources. If the clock is generated
from another type of source (by gating, dividing, or other method),
it should be retimed by the original clock at the last step.
Most of the power dissipated by the AD9243 is from the analog
power supply. However, lower clock speeds will reduce digital
current slightly. Figure 44 shows the relationship between power
and clock rate.
CLOCK FREQUENCY – MHz
125
120
105
6
POWER – mW
5
115
110
5V p-p
2V p-p
100
95
90
43210
Figure 44. AD9243 Power Consumption vs. Clock
Frequency
AD9243
REV. A
–19–
GROUNDING AND DECOUPLING
Analog and Digital Grounding
Proper grounding is essential in any high speed, high resolution
system. Multilayer printed circuit boards (PCBs) are recom-
mended to provide optimal grounding and power schemes. The
use of ground and power planes offers distinct advantages:
1. The minimization of the loop area encompassed by a signal
and its return path.
2. The minimization of the impedance associated with ground
and power paths.
3. The inherent distributed capacitor formed by the power
plane, PCB insulation, and ground plane.
These characteristics result in both a reduction of electro-
magnetic interference (EMI) and an overall improvement in
performance.
It is important to design a layout that prevents noise from coupling
onto the input signal. Digital signals should not be run in paral-
lel with input signal traces and should be routed away from the
input circuitry. While the AD9243 features separate analog and
digital ground pins, it should be treated as an analog compo-
nent. The AVSS, DVSS and DRVSS pins must be joined together
directly under the AD9243. A solid ground plane under the A/D is
acceptable if the power and ground return currents are managed
carefully. Alternatively, the ground plane under the A/D may
contain serrations to steer currents in predictable directions
where cross-coupling between analog and digital would other-
wise be unavoidable. The AD9243/EB ground layout, shown in
Figure 54, depicts the serrated type of arrangement. The analog
and digital grounds are connected by a jumper below the A/D.
Analog and Digital Supply Decoupling
The AD9243 features separate analog and digital supply and
ground pins, helping to minimize digital corruption of sensitive
analog signals.
FREQUENCY – kHz
120
PSRR – dBFS
100
1000
80
60
40
100101
AVDD
DVDD
Figure 45. AD9243 PSSR vs. Frequency
Figure 45 shows the power supply rejection ratio vs. frequency
for a 200 mV p-p ripple applied to both AVDD and DVDD.
In general, AVDD, the analog supply, should be decoupled to
AVSS, the analog common, as close to the chip as physically
possible. Figure 46 shows the recommended decoupling for the
analog supplies; 0.1 µF ceramic chip capacitors should provide
adequately low impedance over a wide frequency range. Note
that the AVDD and AVSS pins are co-located on the AD9243
to simplify the layout of the decoupling capacitors and provide
the shortest possible PCB trace lengths. The AD9243/EB power
plane layout, shown in Figure 55 depicts a typical arrangement
using a multilayer PCB.
0.1mF
AVDD
AVSS
AD9243
0.1mF
AVDD
AVSS
Figure 46. Analog Supply Decoupling
The CML is an internal analog bias point used internally by the
AD9243. This pin must be decoupled with at least a 0.1 µF
capacitor as shown in Figure 47. The dc level of CML is ap-
proximately AVDD/2. This voltage should be buffered if it is to
be used for any external biasing.
0.1mF
CML
AD9243
Figure 47. CML Decoupling
The digital activity on the AD9243 chip falls into two general
categories: correction logic, and output drivers. The internal
correction logic draws relatively small surges of current, mainly
during the clock transitions. The output drivers draw large
current impulses while the output bits are changing. The size
and duration of these currents are a function of the load on the
output bits: large capacitive loads are to be avoided. Note that
the internal correction logic of the AD9243 is referenced DVDD
while the output drivers are referenced to DRVDD.
The decoupling shown in Figure 48, a 0.1 µF ceramic chip
capacitor, is appropriate for a reasonable capacitive load on the
digital outputs (typically 20 pF on each pin). Applications
involving greater digital loads should consider increasing the
digital decoupling proportionally, and/or using external buffers/
latches.
0.1mF
DVDD
DVSS
AD9243
DRVDD
DRVSS
0.1mF
Figure 48. Digital Supply Decoupling
A complete decoupling scheme will also include large tantalum
or electrolytic capacitors on the PCB to reduce low-frequency
ripple to negligible levels. Refer to the AD9243/EB schematic
and layouts in Figures 51–55 for more information regarding the
placement of decoupling capacitors.
AD9243
REV. A
–20–
APPLICATIONS
DIRECT IF DOWN CONVERSION USING THE AD9243
As previously noted, the AD9243’s performance in the differen-
tial mode of operation extends well beyond its baseband region
and into several Nyquist zone regions. Hence, the AD9243 may
be well suited as a mix down converter in both narrow and
wideband applications. Various IF frequencies exist over the
frequency range in which the AD9243 maintains excellent dy-
namic performance (e.g., refer to Figure 5 and 6). The IF sig-
nal will be aliased to the ADC’s baseband region due to the
sampling process in a similar manner that a mixer will down
convert an IF signal. For signals in various Nyquist zones, the
following equation may be used to determine the final frequency
after aliasing.
f
1 NYQUIST
= f
SIGNAL
f
2 NYQUIST
= f
SAMPLE
– f
SIGNAL
f
3 NYQUIST
= abs (f
SAMPLE
– f
SIGNAL
)
f
4 NYQUIST
= 2 × f
SAMPLE
– f
SIGNAL
f
5 NYQUIST
= abs (2 × f
SAMPLE
– f
SIGNAL
)
There are several potential benefits in using the ADC to alias
(i.e., mix) down a narrowband or wideband IF signal. First and
foremost is the elimination of a complete mixer stage with its
associated amplifiers and filters, reducing cost and power dissi-
pation. Second is the ability to apply various DSP techniques to
perform such functions as filtering, channel selection, quadra-
ture demodulation, data reduction, and detection.
One common example is the digitization of a 10.7 MHz IF using a
low jitter 2.5 MHz sample clock. Using the equation above for
the fifth Nyquist zone, the resultant frequency after sampling is
700 kHz. Figure 49 shows the typical performance of the
AD9243 operating under these conditions. Figure 50 demon-
strates how the AD9243 is still able to maintain a high degree of
linearity and SFDR over a wide amplitude.
FREQUENCY – MHz
0
–150
1.25
–15
–75
–105
–135
–30
–45
–90
–120
–60
0
1
AMPLITUDE – dB
7
4
2
9
Figure 49. IF Sampling a 10.7 MHz Input Using the
AD9243 (V
CM
= 2.5 V, Input Span = 2 V p-p)
AIN – dBFS
SFDR – dBc AND dBFS
110
40
–60 0–50 –40 –30 –20 –10
100
90
80
60
50
70
SFDR – dBc
SFDR – dBFS
Figure 50. AD9243 Differential Input SNR/SFDR vs.
Input Amplitude (AIN) @ 10.7 MHz
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AD9243ASZRL

Mfr. #:
Buy AD9243ASZRL
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC Complete 14B 3 MSPS Monolithic
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