PIN # PIN NAME TYPE DESCRIPTION
1 CKPWRGD_PD# IN
3.3V Input notifies device to sample latched inputs and start up on first high
assertion, or exit Power Down Mode on subsequent assertions. Low enters
Power Down Mode.
2 GND GND Ground pin.
3VDDR PWR
3.3V power for differential input clock (receiver). This VDD should be
treated as an analog power rail and filtered appropriately.
4 DIF_IN IN 0.7 V Differential True input
5 DIF_IN# IN 0.7 V Differential Complementary Input
6 SMBDAT I/O Data pin of SMBUS circuitry, 5V tolerant
7 SMBCLK IN Clock pin of SMBUS circuitry, 5V tolerant
8 DFB_OUT_NC# OUT
Complementary half of differential feedback output, provides feedback
signal to the PLL for synchronization with input clock to eliminate phase
error. This pin should NOT be connected on the circuit board, the feedback
is internal to the package.
9 DFB_OUT_NC OUT
True half of differential feedback output, provides feedback signal to the
PLL for synchronization with the input clock to eliminate phase error. This
pin should NOT be connected on the circuit board, the feedback is internal
to the package.
10 VDD PWR Power supply, nominal 3.3V
11 vOE0# IN
Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
12 NC N/A No Connection.
13 DIF_0 OUT 0.7V differential true clock output
14 DIF_0# OUT 0.7V differential Complementary clock output
15 VDD PWR Power supply, nominal 3.3V
16 DIF_1 OUT 0.7V differential true clock output
17 DIF_1# OUT 0.7V differential Complementary clock output
18 vOE1# IN
Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
19 VDD PWR Power supply, nominal 3.3V
20 NC N/A No Connection.
21 DIF_2 OUT 0.7V differential true clock output
22 DIF_2# OUT 0.7V differential Complementary clock output
23 vOE2# IN
Active low input for enabling DIF pair 2. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
24 vOE3# IN
Active low input for enabling DIF pair 3. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
25 DIF_3 OUT 0.7V differential true clock output
26 DIF_3# OUT 0.7V differential Complementary clock output
27 VDD PWR Power supply, nominal 3.3V
28 DIF_4 OUT 0.7V differential true clock output
29 DIF_4# OUT 0.7V differential Complementary clock output
30 vOE4# IN
Active low input for enabling DIF pair 4. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
31 vOE5# IN
Active low input for enabling DIF pair 5. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
