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9ZXL0831AKLFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
9ZXL0831
8-OUTPUT DB800ZL
IDT®
8-OUTPUT DB800ZL 4
9ZXL0831 REV E 081616
Pin Descriptions (cont.)
PIN # PIN NAME TYPE DESCRIPTION
32 DIF_5 OUT 0.7V differential true clock output
33 DIF_5# OUT 0.7V differential Complementary clock output
34 VDD PWR Power supply, nominal 3.3V
35 DIF_6 OUT 0.7V differential true clock output
36 DIF_6# OUT 0.7V differential Complementary clock output
37 vOE6# IN
Active low input for enabling DIF pair 6. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
38 VDD PWR Power supply, nominal 3.3V
39 DIF_7 OUT 0.7V differential true clock output
40 DIF_7# OUT 0.7V differential Complementary clock output
41 vOE7# IN
Active low input for enabling DIF pair 7. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
42 VDD PWR Power supply, nominal 3.3V
43 NC N/A No Connection.
44 VDDA PWR 3.3V power for the PLL core.
45 NC N/A No Connection.
46 NC N/A No Connection.
47 100M_133M# IN
3.3V Input to select operating frequency.
See Functionality Table for Definition
48 HIBW_BYPM_LOBW# IN
Trilevel input to select High BW, Bypass or Low BW mode.
See PLL Operating Mode Table for Details.
49 GND PWR Ground
9ZXL0831
8-OUTPUT DB800ZL
IDT®
8-OUTPUT DB800ZL 5
9ZXL0831 REV E 081616
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9ZXL0831. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over
the recommended operating temperature range.
Electrical Characteristics–DIF_IN Clock Input Parameters (HCSL-compatible)
PARAMETER SYMBOL CONDITIONS
MIN TYP MAX
UNITS NOTES
3.3V Supply Voltage
VDD, VDDA,
VDDR
VDD for core logic and PLL 4.6 V 1,2
Input Low Voltage V
IL
GND-0.5 V 1
Input High Voltage V
IH
Except for SMBus interface V
DD
+0.5V V 1
Input High Voltage V
IHSMB
SMBus clock and data pins 5.5V V 1
Storage Temperature Ts -65 150
°
C
1
Junction Temperature Tj 125 °C
1
Input ESD protection
ESD prot Human Body Model 2000 V 1
1
Guaranteed by design and characterization, not 100% tested in production.
2
Operation under these conditions is neither implied nor
g
uaranteed.
T
A
= T
COM
; Supply Voltage V
DD
= 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Input Crossover Voltage -
DIF_IN
V
CROSS
Cross Over Voltage 150 900 mV 1
Input Swing - DIF_IN V
SWING
Differential value 300 mV 1
Input Slew Rate - DIF_IN dv/dt Measured differentially 0.4 8 V/ns 1,2
Input Leakage Current I
IN
V
IN
= V
DD ,
V
IN
=
GND -5 5 uA
Input Duty Cycle d
tin
Measurement from differential wavefrom 45 55 % 1
Input Jitter - Cycle to Cycle J
DIFIn
Differential Measurement 0 125 ps 1
1
Guaranteed by design and characterization, not 100% tested in production.
2
Slew rate measured throu
g
h +/-75mV window centered around differential zero
9ZXL0831
8-OUTPUT DB800ZL
IDT®
8-OUTPUT DB800ZL 6
9ZXL0831 REV E 081616
Electrical Characteristics–Input/Supply/Common Parameters
T
A
= T
COM
; Supply Voltage V
DD
= 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Ambient Operating
Temperature
T
COM
Commmercial range 0 70 °C 1
Input High Voltage V
IH
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
2V
DD
+ 0.3 V 1
Input Low Voltage V
IL
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
GND
- 0.3 0.8 V 1
I
IN
Single-ended inputs, V
IN
= GND, V
IN
= VDD -5 5 uA 1
I
INP
Single-ended inputs
V
IN
= 0 V; Inputs with internal pull-up resistors
V
IN
= VDD; Inputs with internal pull-down resistors
-200 200 uA 1
F
ib
yp
V
DD
= 3.3 V, Bypass mode 33 150 MHz 2
F
i
p
ll
V
DD
= 3.3 V, 100MHz PLL mode 90 100.00 110 MHz 2
F
i
p
ll
V
DD
= 3.3 V, 133.33MHz PLL mode 120 133.33 147 MHz 2
Pin Inductance L
p
in
7nH1
C
IN
Logic Inputs, except DIF_IN 1.5 5 pF 1
C
INDIF_IN
DIF_IN differential clock inputs 1.5 2.7 pF 1,4
C
OUT
Output pin capacitance 6 pF 1
Clk Stabilization T
STAB
From V
DD
Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
0.250 1 ms 1,2
Input SS Modulation
Frequency
f
MODI N
Allowable Frequency
(Triangular Modulation)
30 33 kHz 1
OE# Latency t
LATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
4 12 cycles 1,3
Tdrive_PD# t
DRVPD
DIF output enable after
PD# de-assertion
300 us 1,3
Tfall t
F
Fall time of control inputs 10 ns 1,2
Trise t
R
Rise time of control inputs 10 ns 1,2
SMBus Input Low Voltage V
ILSMB
0.8 V 1
SMBus Input High Voltage V
IHSMB
2.1 V
DDSMB
V1
SMBus Output Low Voltage V
OLSMB
@ I
PULLUP
0.4 V 1
SMBus Sink Current I
PULLUP
@ V
OL
4mA1
Nominal Bus Voltage V
DDSMB
3V to 5V +/- 10% 2.7 5.5 V 1
SCLK/SDATA Rise Time t
RSMB
(Max VIL - 0.15) to (Min VIH + 0.15) 1000 ns 1
SCLK/SDATA Fall Time t
FSMB
(Min VIH + 0.15) to (Max VIL - 0.15) 300 ns 1
SMBus Operating
Frequency
f
MAXSMB
Maximum SMBus operating frequency 100 kHz 1,5
1
Guaranteed by desi
g
n and characterization, not 100% tested in production.
2
Control input must be monotonic from 20% to 80% of input swin
g
.
5
The differential input clock must be running for the SMBus to be active
Input Current
3
Time from deassertion until outputs are >200 mV
4
DIF_IN input
Capacitance
Input Frequency
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

9ZXL0831AKLFT

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Description:
Clock Buffer HIGH PERF. ZDB
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