9ZXL0831
8-OUTPUT DB800ZL
IDT®
8-OUTPUT DB800ZL 10
9ZXL0831 REV E 081616
Clock Periods–Differential Outputs with Spread Spectrum Disabled
Clock Periods–Differential Outputs with Spread Spectrum Enabled
Test Loads
1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock
-c2c jitter
AbsPer
Min
-SSC
Short-Term
Average
Min
- ppm
Long-Term
Average
Min
0 ppm
Period
Nominal
+ ppm
Long-Term
Average
Ma
x
+SSC
Short-Term
Average
Ma
x
+c2c jitter
AbsPer
Max
100.00 9.94900 9.99900 10.00000 10.00100 10.05100 ns 1,2,3
133.33 7.44925 7.49925 7.50000 7.50075 7.55075 ns 1,2,4
SSC OFF
DIF
Measurement Window
Units Notes
Center
Freq.
MHz
1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock
-c2c jitter
AbsPer
Min
-SSC
Short-Term
Average
Min
- ppm
Long-Term
Average
Min
0 ppm
Period
Nominal
+ ppm
Long-Term
Average
Ma
x
+SSC
Short-Term
Average
Ma
x
+c2c jitter
AbsPer
Max
99.75 9.94906 9.99906 10.02406 10.02506 10.02607 10.05107 10.10107 ns 1,2,3
133.00 7.44930 7.49930 7.51805 7.51880 7.51955 7.53830 7.58830 ns 1,2,4
Notes:
1
Guaranteed by design and characterization, not 100% tested in production.
3
Driven by SRC output of main clock, 100 MHz PLL Mode or Bypass mode
4
Driven by CPU output of main clock, 133 MHz PLL Mode or Bypass mode
Notes
2
All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK420BQ/CK410B+
accuracy requirements (+/-100ppm). The device itself does not contribute to ppm error.
DIF
Measurement Window
UnitsSSC ON
Center
Freq.
MHz
Differential Output Terminations
DIF Zo (
)Rs (
)
100 33
85 27
85ohm Differential Zo
Low-Power
HCSL-
Compatible
Output buffer
Differential Test Loads
Rs
Rs
2pF 2pF
10 inches
9ZXL0831
8-OUTPUT DB800ZL
IDT®
8-OUTPUT DB800ZL 11
9ZXL0831 REV E 081616
General SMBus Serial Interface Information for 9ZXL0831
How to Write
Controller (host) sends a start bit
Controller (host) sends the write address
IDT clock will acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will acknowledge
Controller (host) sends the byte count = X
IDT clock will acknowledge
Controller (host) starts sending Byte N through Byte
N+X-1
IDT clock will acknowledge each byte one at a time
Controller (host) sends a Stop bit
How to Read
Controller (host) will send a start bit
Controller (host) sends the write address
IDT clock will acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will acknowledge
Controller (host) will send a separate start bit
Controller (host) sends the read address
IDT clock will acknowledge
IDT clock will send the data byte count = X
IDT clock sends Byte N+X-1
IDT clock sends Byte 0 through Byte X (if X
(H)
was
written to Byte 8)
Controller (host) will need to acknowledge each byte
Controller (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) IDT (Slave/Receiver)
TstarT bit
Slave Address
WR WRite
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
X Byte
ACK
O
O O
O O
O
Byte N + X - 1
ACK
PstoP bit
Index Block Read Operation
Controller (Host) IDT (Slave/Receiver)
TstarT bit
Slave Address
WR WRite
ACK
Beginning Byte = N
ACK
RT Repeat starT
Slave Address
RD ReaD
ACK
Data Byte Count=X
ACK
X Byte
Beginning Byte N
ACK
O
O O
O O
O
Byte N + X - 1
N Not acknowledge
PstoP bit
9ZXL0831
8-OUTPUT DB800ZL
IDT®
8-OUTPUT DB800ZL 12
9ZXL0831 REV E 081616
SMBusTable: PLL Mode, and Frequency Select Register
Pin
#
Name Control Function T
yp
e 0 1 Default
Bit 7
PLL Mode 1 PLL O
p
eratin
g
Mode Rd back 1
R
Latch
Bit 6
PLL Mode 0 PLL O
p
eratin
g
Mode Rd back 0
R
Latch
Bit 5
0
Bit 4
0
Bit 3
PLL_SW_EN Enable S/W control of PLL BW R
W
HW Latch SMBus Control 0
Bit 2
PLL Mode 1 PLL O
p
eratin
g
Mode 1 R
W
1
Bit 1
PLL Mode 0 PLL O
p
eratin
g
Mode 0 R
W
1
Bit 0
100M_133M# Fre
q
uenc
y
Select Readback
R
133MHz 100MHz
Latch
SMBusTable: Output Control Register
Pin
#
Name Control Function T
yp
e 0 1 Default
Bit 7
DIF_5_En Out
p
ut Control - '0' overrides OE#
p
in R
W
1
Bit 6
DIF_4_En Out
p
ut Control - '0' overrides OE#
p
in R
W
1
Bit 5
DIF_3_En Out
p
ut Control - '0' overrides OE#
p
in R
W
1
Bit 4
DIF_2_En Out
p
ut Control - '0' overrides OE#
p
in R
W
1
Bit 3
1
Bit 2
DIF_1_En Out
p
ut Control - '0' overrides OE#
p
in R
W
1
Bit 1
DIF_0_En Out
p
ut Control - '0' overrides OE#
p
in R
W
1
Bit 0
1
SMBusTable: Output Control Register
Pin
#
Name Control Function T
yp
e 0 1 Default
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
1
Bit 2
DIF_7_En Out
p
ut Control - '0' overrides OE#
p
in R
W
Low/Low Enable 1
Bit 1
1
Bit 0
DIF_6_En Out
p
ut Control - '0' overrides OE#
p
in R
W
Low/Low Enable 1
SMBusTable: Reserved Register
Pin
#
Name Control Function T
yp
e 0 1 Default
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
SMBusTable: Reserved Register
Pin
#
Name Control Function T
yp
e 0 1 Default
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
Reserved
Low/Low Enable
Low/Low Enable
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
B
y
te 3
35/36
21/22
47
B
y
te 1
B
y
te 2
28/29
25/26
B
y
te 4
16/17
13/14
B
y
te 0
48
48
32/33
39/40
See PLL Operating Mode
Readback Table
See PLL Operating Mode
Readback Table
Note:
Setting bit 3 to '1' allows the user to overide the Latch value from pin 5 via use of bits 2 and 1. Use the values from the PLL Operating
Mode Readback Table. Note that Bits 7 and 6 will keep the value originally latched on pin 5. A warm reset of the system will have to
accomplished if the user changes these bits.
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved

9ZXL0831AKLFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer HIGH PERF. ZDB
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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