9ZXL0831
8-OUTPUT DB800ZL
IDT®
8-OUTPUT DB800ZL 7
9ZXL0831 REV E 081616
Electrical Characteristics–DIF 0.7V Low Power Differential Outputs
Electrical Characteristics–Current Consumption
T
A
= T
COM
; Supply Voltage V
DD
= 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Slew rate Trf Scope avera
g
in
g
on 2 3.3 4
V/ns
1, 2, 3
Slew rate matching
Trf Slew rate matching, Scope averaging on 6.8 20
%
1, 2, 4
Voltage High VHigh 660 778 850 1
Voltage Low VLow -150 0 150 1
Max Voltage Vmax 918 1150 1
Min Voltage Vmin -300 -71 1
Vswing Vswing Scope averaging off 300 1556 1812 mV 1, 2
Crossing Voltage (abs) Vcross_abs Scope averaging off 300 458 550 mV 1, 5
Crossing Voltage (var)
-Vcross Scope averaging off 17 140 mV 1, 6
2
Measured from differential waveform
6
The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross
absolute) allowed. The intent is to limit Vcross induced modulation by setting
-Vcross to be smaller than Vcross absolute.
mV
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope
averaging on)
Measurement on single ended signal using
absolute value. (Scope averaging off)
mV
1
Guaranteed by design and characterization, not 100% tested in production. C
L
= 2pF with R
S
= 27
for Zo = 85
differential trace
impedance).
3
Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4
Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5
Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
T
A
= T
COM
; Supply Voltage V
DD
= 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
I
DDVDD
133MHz, VDD rail
59
75 mA 1
I
DDVDDA
133MHz, VDDA + VDDR rail, PLL Mode
19
25 mA 1
I
DDVDDPD
Power Down, VDD Rail
1.2
2mA1
I
DDVDDAPD
Power Down, VDDA Rail
2.5
5mA1
1
Guaranteed by desi
g
n and characterization, not 100% tested in production.
2
C
L
= 2pF with R
S
= 27
for Zo = 85
differential trace impedance
Operating Current
Powerdown Current
9ZXL0831
8-OUTPUT DB800ZL
IDT®
8-OUTPUT DB800ZL 8
9ZXL0831 REV E 081616
Electrical Characteristics–Skew and Differential Jitter Parameters
T
A
= T
COM
; Supply Voltage V
DD
= 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
CLK_IN, DIF[x:0] t
SPO_PLL
Input-to-Output Skew in PLL mode
nominal value @ 25°C, 3.3V
-100 -60 100 ps 1,2,4,5,8
CLK_IN, DIF[x:0] t
PD_BYP
Input-to-Output Skew in Bypass mode
nominal value @ 25°C, 3.3V
2.5 3.2 4.5 ns 1,2,3,5,8
CLK_IN, DIF[x:0] t
DSPO_PLL
Input-to-Output Skew Varation in PLL mode
across volta
g
e and temperature
-50 50 ps 1,2,3,5,8
CLK_IN, DIF[x:0] t
DSPO_BYP
Input-to-Output Skew Varation in Bypass mode
across voltage and temperature
-250 250 ps 1,2,3,5,8
CLK_IN, DIF[x:0] t
DTE
Random Differential Tracking error beween two
9ZX devices in Hi BW Mode
15
ps
(rms)
1,2,3,5,8
CLK_IN, DIF[x:0] t
DSSTE
Random Differential Spread Spectrum Tracking
error beween two 9ZX devices in Hi BW Mode
5 75 ps 1,2,3,5,8
DIF{x:0] t
SKEW_ALL
Output-to-Output Skew across all outputs
(Common to Bypass and PLL mode)
53 65 ps 1,2,3,8
PLL Jitter Peaking j
p
eak-hibw
LOBW#_BYPASS_HIBW = 1 0 1.2 2.5 dB 7,8
PLL Jitter Peaking j
p
eak-lobw
LOBW#_BYPASS_HIBW = 0 0 0.76 2 dB 7,8
PLL Bandwidth pll
HI BW
LOBW#_BYPASS_HIBW = 1 2 3 4 MHz 8,9
PLL Bandwidth pll
LOBW
LOBW#_BYPASS_HIBW = 0 0.7 1.1 1.4 MHz 8,9
Duty Cycle t
D
C
Measured differentially, PLL Mode 45 50.1 55 % 1
Duty Cycle Distortion t
DCD
Measured differentially, Bypass Mode
@100MHz
-2 0 2 % 1,10
PLL mode 34 50 ps 1,11
Additive Jitter in Bypass Mode 17 50 ps 1,11
Notes for preceding table:
6.
t is the period of the input clock
7
Measured as maximum pass band
g
ain. At frequencies within the loop BW, hi
g
hest point of ma
g
nification is called PLL jitter peakin
g
.
8.
Guaranteed by design and characterization, not 100% tested in production.
9
Measured at 3 db down or half power point.
10
Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.
11
Measured from differential waveform
Jitter, Cycle to cycle t
jcyc-cyc
1
C
L
= 2pF with RS = 27
for Zo = 85
differential trace impedance. Input to output skew is measured at the first output edge following the
corresponding input.
2
Measured from differential cross-
p
oint to differential cross-
p
oint. This
p
arameter can be tuned with external feedback
p
ath
,
if
p
resent.
3
All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it.
4
This parameter is deterministic for a given device
5
Measured with scope averaging on to find mean value.
9ZXL0831
8-OUTPUT DB800ZL
IDT®
8-OUTPUT DB800ZL 9
9ZXL0831 REV E 081616
Electrical Characteristics–Phase Jitter Parameters
T
A
= T
COM
; Supply Voltage V
DD
= 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes
t
jphPCIeG1
PCIe Gen 1 34 86 ps (p-p) 1,2,3
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
1.2 3
ps
(rms)
1,2
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
2.2
3.1
ps
(rms)
1,2
t
jphPCIeG3
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz)
0.5
1
ps
(rms)
1,2,4
QPI & SMI
(100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI)
0.24 0.5
ps
(rms)
1,5
QPI & SMI
(100MHz, 8.0Gb/s, 12UI)
0.14 0.3
ps
(rms)
1,5
QPI & SMI
(100MHz, 9.6Gb/s, 12UI)
0.12 0.2
ps
(rms)
1,5
t
jp
hPCIeG1
PCIe Gen 1 3.7 10 ps (p-p) 1,2,3
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
0.1 0.3
ps
(rms)
1,2,6
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
0.4 0.6
ps
(rms)
1,2,6
t
jphPCIeG3
PCIe Gen 3
(PLL BW of 2-4MHz, 2-5MHz, CDR = 10MHz)
0.00
0.2
ps
(rms)
1,2,4,6
QPI & SMI
(100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI)
0.14 0.2
ps
(rms)
1,5,6
QPI & SMI
(100MHz, 8.0Gb/s, 12UI)
0.00 0.1
ps
(rms)
1,5,6
QPI & SMI
(100MHz, 9.6Gb/s, 12UI)
0.00 0.1
ps
(rms)
1,5,6
1
Applies to all outputs.
6
For RMS figures, additive jitter is calculated by solving the following equation: (Additive jitter)^2 = (total jittter)^2 - (input jitter)^2
4
Subject to final ratification by PCI SIG.
5
Calculated from Intel-supplied Clock Jitter Tool v 1.6.3
2
See http://www.pcisig.com for complete specs
Additive Phase Jitter,
Bypass mode
t
jphPCIeG2
t
jphQPI_SMI
3
Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
t
jphQPI_SMI
Phase Jitter, PLL Mode
t
jphPCIeG2

9ZXL0831AKLFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer HIGH PERF. ZDB
Lifecycle:
New from this manufacturer.
Delivery:
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