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PCF8564AU/5BB/1,01

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48
PCF8564A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 26 August 2013 13 of 48
NXP Semiconductors
PCF8564A
Real time clock and calendar
As a consequence of this method, it is very important to make a read or write access in
one go, that is, setting or reading seconds through to years should be made in one single
access. Failing to comply with this method could result in the time becoming corrupted.
As an example, if the time (seconds through to hours) is set in one access and then in a
second access the date is set, it is possible that the time may increment between the two
accesses. A similar problem exists when reading. A roll over may occur between reads
thus giving the minutes from one moment and the hours from the next.
Recommended method for reading the time:
1. Send a START condition and the slave address for write (A2h).
2. Set the address pointer to 2 (seconds) by sending 02h.
3. Send a RE-START condition or STOP followed by START.
4. Send the slave address for read (A3h).
5. Read the seconds.
6. Read the minutes.
7. Read the hours.
8. Read the days.
9. Read the weekdays.
10. Read the century and month.
11. Read the years.
12. Send a STOP condition.
8.6 Alarm registers
8.6.1 Register Minute_alarm
[1] Default value.
Fig 6. Access time for read/write operations
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Table 19. Minute_alarm - minute alarm register (address 09h) bit description
Bit Symbol Value Place value Description
7 AEN_M 0 - minute alarm is enabled
1
[1]
- minute alarm is disabled
6 to 4 MINUTE_ALARM 0 to 5 ten’s place minute alarm information coded in BCD
format
3 to 0 0 to 9 unit place
PCF8564A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 26 August 2013 14 of 48
NXP Semiconductors
PCF8564A
Real time clock and calendar
8.6.2 Register Hour_alarm
[1] Default value.
8.6.3 Register Day_alarm
[1] Default value.
8.6.4 Register Weekday_alarm
[1] Default value.
8.6.5 Alarm flag
By clearing the MSB of one or more of the alarm registers AEN_x (Alarm Enable), the
corresponding alarm condition(s) are active. When an alarm occurs, AF is set to logic 1.
The asserted AF can be used to generate an interrupt (INT
). The AF is cleared by
command.
The registers at addresses 09h through 0Ch contain alarm information. When one or
more of these registers is loaded with a valid minute, hour, day, or weekday and its
corresponding Alarm Enable bit (AEN_x) is logic 0, then that information is compared with
the current minute, hour, day, and weekday. When all enabled comparisons first match,
the Alarm Flag (AF in register Control_2) is set to logic 1.
Table 20. Hour_alarm - hour alarm register (address 0Ah) bit description
Bit Symbol Value Place value Description
7 AEN_H 0 - hour alarm is enabled
1
[1]
- hour alarm is disabled
6 - - - unused
5 to 4 HOUR_ALARM 0 to 2 ten’s place hour alarm information coded in BCD
format
3 to 0 0 to 9 unit place
Table 21. Day_alarm - day alarm register (address 0Bh) bit description
Bit Symbol Value Place value Description
7 AEN_D 0 - day alarm is enabled
1
[1]
- day alarm is disabled
6 - - - unused
5 to 4 DAY_ALARM 0 to 3 ten’s place day alarm information coded in BCD
format
3 to 0 0 to 9 unit place
Table 22. Weekday_alarm - weekday alarm register (address 0Ch) bit description
Bit Symbol Value Description
7 AEN_W 0 weekday alarm is enabled
1
[1]
weekday alarm is disabled
6 to 3 - - unused
2 to 0 WEEKDAY_ALARM 0 to 6 weekday alarm information coded in BCD format
PCF8564A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 26 August 2013 15 of 48
NXP Semiconductors
PCF8564A
Real time clock and calendar
The generation of interrupts from the alarm function is controlled via bit AIE. If bit AIE is
enabled, the INT
pin follows the condition of bit AF. AF will remain set until cleared by
command. Once AF has been cleared, it will only be set again when the time increments
to match the alarm condition once more. Alarm registers which have their AEN_x bit at
logic 1 are ignored.
8.7 Register CLKOUT_ctrl and clock output
A programmable square wave is available at pin CLKOUT. Operation is controlled by the
FE bit in register CLKOUT_ctrl at address 0Dh and the CLKOUT output enable pin
(CLKOE). To enable pin CLKOUT pin CLKOE must be set HIGH.
Frequencies of 32.768 kHz (default), 1.024 kHz, 32 Hz, and 1 Hz can be generated for
use as a system clock, microcontroller clock, input to a charge pump, or for calibration of
the oscillator.
(1) Only when all enabled alarm settings are matching.
It’s only on increment to a matched case that the alarm flag is set, see Section 8.6.5
.
Fig 7. Alarm function block diagram
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P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48

PCF8564AU/5BB/1,01

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Manufacturer:
NXP Semiconductors
Description:
IC RTC CLK/CALENDAR I2C DIE
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