PCF8564A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
Product data sheet Rev. 3 — 26 August 2013 31 of 48
NXP Semiconductors
PCF8564A
Real time clock and calendar
15. Dynamic characteristics
[1] Integrated load capacitance, C
L(itg)
, is a calculation of C
OSCI
and C
OSCO
in series: .
[2] Unspecified for f
CLKOUT
= 32.768 kHz.
[3] All timing values are valid within the operating supply voltage at ambient temperature and referenced to V
IL
and V
IH
with an input voltage
swing of V
SS
to V
DD
.
[4] A detailed description of the I
2
C-bus specification is given in Ref. 9 “UM10204”.
Table 31. Dynamic characteristics
V
DD
= 1.8 V to 5.5 V; V
SS
=0V; T
amb
=
40
C to +85
C; f
osc
= 32.768 kHz; quartz R
s
=40k
; C
L
= 8 pF; unless otherwise
specified.
Symbol Parameter Conditions Min Typ Max Unit
Oscillator
C
L(itg)
integrated load capacitance
[1]
6810pF
f
osc
/f
osc
relative oscillator frequency
variation
V
DD
=200mV;
T
amb
=25C
-0.2-ppm
Quartz crystal parameters
R
s
series resistance - - 100 k
C
L
load capacitance - 8 - pF
CLKOUT output
CLKOUT
duty cycle on pin CLKOUT
[2]
-50-%
I
2
C-bus timing characteristics (see Figure 25)
[3][4]
f
SCL
SCL clock frequency - - 400 kHz
t
HD;STA
hold time (repeated) START
condition
0.6 - - s
t
SU;STA
set-up time for a repeated START
condition
0.6 - - s
t
LOW
LOW period of the SCL clock 1.3 - - s
t
HIGH
HIGH period of the SCL clock 0.6 - - s
t
r
rise time of both SDA and SCL
signals
--0.3s
t
f
fall time of both SDA and SCL
signals
--0.3s
C
b
capacitive load for each bus line - - 400 pF
t
SU;DAT
data set-up time 100 - - ns
t
HD;DAT
data hold time 0 - - ns
t
SU;STO
set-up time for STOP condition 0.6 - - s
t
w(spike)
spike pulse width - - 50 ns
C
Litg
C
OSCI
C
OSCO
C
OSCI
C
OSCO
+
--------------------------------------------
=