IDT5V49EE901
EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER
IDT®
EEPROM PROGRAMMABLE CLOCK GENERATOR 16
IDT5V49EE901 REV S 071015
I
2
C Bus DC Characteristics
I
2
C Bus AC Characteristics for Standard Mode
Note 1: A device must internally provide a hold time of at least 300 ns for the SDAT signal (referred to the V
IH
(MIN)
of the SCLK signal) to bridge the undefined region of the falling edge of SCLK.
Symbol Parameter Conditions Min Typ Max Unit
V
IH
Input HIGH Level 0.7xV
DD
V
V
IL
Input LOW Level 0.3xV
DD
V
V
HYS
Hysteresis of Inputs 0.05xV
DD
V
I
IN
Input Leakage Current ±1.0 µA
V
OL
Output LOW Voltage I
OL
= 3 mA 0.4 V
Symbol Parameter Min Typ Max Unit
F
SCLK
Serial Clock Frequency (SCL) 0 100 kHz
t
BUF
Bus free time between STOP and START 4.7 µs
t
SU:START
Setup Time, START 4.7 µs
t
HD:START
Hold Time, START 4 µs
t
SU:DATA
Setup Time, data input (SDA) 250 ns
t
HD:DATA
Hold Time, data input (SDA)
1
s
t
OVD
Output data valid from clock 3.45 µs
C
B
Capacitive Load for Each Bus Line 400 pF
t
R
Rise Time, data and clock (SDAT, SCLK) 1000 ns
t
F
Fall Time, data and clock (SDAT, SCLK) 300 ns
t
HIGH
HIGH Time, clock (SCLK) 4 µs
t
LOW
LOW Time, clock (SCLK) 4.7 µs
t
SU:STOP
Setup Time, STOP 4 µs
IDT5V49EE901
EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER
IDT®
EEPROM PROGRAMMABLE CLOCK GENERATOR 17
IDT5V49EE901 REV S 071015
I
2
C Bus AC Characteristics for Fast Mode
Note 1: A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V
IH
(MIN)
of the SCL signal) to bridge the undefined region of the falling edge of SCL.
Symbol Parameter Min Typ Max Unit
F
SCLK
Serial Clock Frequency (SCL) 0 400 kHz
t
BUF
Bus free time between STOP and START 1.3 µs
t
SU:START
Setup Time, START 0.6 µs
t
HD:START
Hold Time, START 0.6 µs
t
SU:DATA
Setup Time, data input (SDA) 100 ns
t
HD:DATA
Hold Time, data input (SDA)
1
s
t
OVD
Output data valid from clock 0.9 µs
C
B
Capacitive Load for Each Bus Line 400 pF
t
R
Rise Time, data and clock (SDA, SCL) 20 + 0.1xC
B
300 ns
t
F
Fall Time, data and clock (SDA, SCL) 20 + 0.1xC
B
300 ns
t
HIGH
HIGH Time, clock (SCL) 0.6 µs
t
LOW
LOW Time, clock (SCL) 1.3 µs
t
SU:STOP
Setup Time, STOP 0.6 µs
IDT5V49EE901
EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER
IDT®
EEPROM PROGRAMMABLE CLOCK GENERATOR 18
IDT5V49EE901 REV S 071015
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the IDT5V49EE901. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any
other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only
over the recommended operating temperature range.
Recommended Operation Conditions
Symbol Description Min Max Unit
V
DD
Internal Power Supply Voltage -0.5 +4.6 V
V
I
Input Voltage
1
1.Input negative and output voltage ratings may be exceeded if the input and output current ratings are observed.
-0.5 +4.6 V
V
O
Output Voltage (not to exceed 4.6 V)
1
-0.5 V
DD
+0.5 V
T
J
Junction Temperature 150 °C
T
STG
Storage Temperature -65 150 °C
Symbol Parameter Min Typ Max Unit
V
DD
Power supply voltage for V
DD
pins supporting core and
outputs
3.135 3.3 3.465 V
V
DDX
Power supply voltage for crystal oscillator. Use filtered
analog power supply if available.
3.135 3.3 3.465 V
AV
DD
Analog power supply voltage. Use filtered analog
power supply if available.
3.135 3.3 3.465 V
T
A
Operating temperature, ambient -40 +85 °C
C
LOAD_OUT
Maximum load capacitance (3.3V LVTTL only) 15 pF
F
IN
External reference crystal 8 50 MHz
External reference clock CLKIN 1 200
t
PU
Power up time for all V
DD
s to reach minimum specified
voltage (power ramps must be monotonic)
0.05 5 ms

5V49EE901PGGI8

Mfr. #:
Manufacturer:
IDT
Description:
Clock Generators & Support Products EEPROM PROGRAMMABLE PLL
Lifecycle:
New from this manufacturer.
Delivery:
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