IDT5V49EE901
EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER
IDT®
EEPROM PROGRAMMABLE CLOCK GENERATOR 23
IDT5V49EE901 REV S 071015
Spread Spectrum Generation Specifications
Test Circuits and Conditions
Test Circuits for DC Outputs
t7 Clock Jitter
6
Peak-to-peak period jitter, 1PLL, multiple
output frequencies switching, LVTTL outputs
80 100 ps
Peak-to-peak period jitter, all 4 PLLs on,
LVTTL outputs
3
200 270 ps
Peak-to-peak period jitter, 1PLL, multiple
output frequencies switching, LVPECL, LVDS
or HCSL outputs
60 80 ps
Peak-to-peak period jitter, all 4 PLLs on,
LVPECL, LVDS or HCSL outputs
120 160 ps
t8 Output Skew Skew between output to output on the same
bank
75 ps
t9
4
Lock Time PLL lock time from power-up 10 20 ms
t10
5
Lock Time PLL lock time from shutdown mode 2 ms
1.Practical lower frequency is determined by loop filter settings.
2.A slew rate of 2.75V/ns or greater should be selected for output frequencies of 100MHz or higher.
3.Jitter measured with clock outputs of 27 MHz, 48 MHz, 24.576 MHz, 74.25 MHz and 25 MHz.
4.Includes loading the configuration bits from EEPROM to PLL registers. It does not include EEPROM programming/write time.
5.Actual PLL lock time depends on the loop configuration.
6. Not guaranteed until customer specific configuration is approved by IDT.
Symbol Parameter Description Min Typ Max Unit
f
IN
1
1.Practical lower frequency is determined by loop filter settings.
2. Not guaranteed until customer specific configuration is approved by IDT.
Input Frequency Input Frequency Limit 1 400 MHz
f
MOD
Mod Frequency Modulation Frequency 33 120 kHz
f
SPREAD
2
Spread Value Amount of Spread Value (programmable) - Down Spread -0.5 -4.0 %f
OUT
Amount of Spread Value (programmable) - Center Spread ±0.25 ±2.0
Symbol Parameter Test Conditions Min. Typ. Max. Units
OUTx
V
DD
CLK
OUT
GND
C
L
0.1µF
V
DDOx
0.1µF
