5V49EE901PGGI8 Datasheet 5V49EE901-064PGGI, 5V49EE901NLGI, 5V49EE901PGGI | P28-P30

IDT5V49EE901

EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER

IDT®

EEPROM PROGRAMMABLE CLOCK GENERATOR 28

IDT5V49EE901 REV S 071015

0x77 00

SLEW2[1:0] CMEN3 CMEN1

CMEN# - common mode enable

Set to 1 for LVDS

Set to 0 for LVTTL, LVPECL,

HCSL

0x78 00

OEM3[1:0] SLEW3[1:0] INV3[1:0] LVL3[1:0]

OEM3 controls OUT3 and OUT6

0x79 00

OEM4[1:0] SLEW4[1:0] INV4[1:0] LVL4[1:0]

OEM4 controls OUT4 and

OUT4b

0x7A 00

OEM5[1:0] SLEW5[1:0] INV5[1:0] LVL5[1:0]

OEM5 controls OUT5 and

OUT5b

0x7B 00

SLEW6[1:0] CMEN5 CMEN4

0x7C XX

Reserved

0x7D XX

Reserved

0x7E XX

Reserved

0x7F XX

Reserved

0x80 00

SSVCO[15:8]_CFG0

PLL3 Spread Spectrum

Feedback Counter

0x81 00

SSVCO[15:8]_CFG1

0x82 00

SSVCO[15:8]_CFG2

0x83 00

SSVCO[15:8]_CFG3

0x84 00

SSVCO[15:8]_CFG4

0x85 00

SSVCO[15:8]_CFG5

0x86 00

Reserved

0x87 00

Reserved

Addr

Default

Hex

Value

Bit #

Description

7654321 0

IDT5V49EE901

EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER

IDT®

EEPROM PROGRAMMABLE CLOCK GENERATOR 29

IDT5V49EE901 REV S 071015

0x88 FF

PM1_CFG0 Q1[6:0]_CFG0

Output Divides

for Q<>111111,

PM=0 - Divide by 2

PM=1, (Q+2)*2

for Q=1111111

PM=0, disable the output divider

PM=1, bypass the output divide,

(divide by 1)

0x89 FF

PM1_CFG1 Q1[6:0]_CFG1

0x8A FF

PM1_CFG2 Q1[6:0]_CFG2

0x8B FF

PM1_CFG3 Q1[6:0]_CFG3

0x8C FF

PM1_CFG4 Q1[6:0]_CFG4

0x8D FF

PM1_CFG5 Q1[6:0]_CFG5

0x8E 7F

PM2_CFG4 Q2[6:0]_CFG4

0x8F 7F

PM2_CFG5 Q2[6:0]_CFG5

0x90 7F

PM2_CFG0 Q2[6:0]_CFG0

0x91 7F

PM2_CFG1 Q2[6:0]_CFG1

0x92 7F

PM2_CFG2 Q2[6:0]_CFG2

0x93 7F

PM2_CFG3 Q2[6:0]_CFG3

0x94 7F

PM3_CFG0 Q3[6:0]_CFG0

0x95 7F

PM3_CFG1 Q3[6:0]_CFG1

0x96 7F

PM3_CFG2 Q3[6:0]_CFG2

0x97 7F

PM3_CFG3 Q3[6:0]_CFG3

0x98 7F

PM3_CFG4 Q3[6:0]_CFG4

0x99 7F

PM3_CFG5 Q3[6:0]_CFG5

0x9A 7F

PM4_CFG4 Q4[6:0]_CFG4

0x9B 7F

PM4_CFG5 Q4[6:0]_CFG5

0x9C 7F

PM4_CFG0 Q4[6:0]_CFG0

0x9D 7F

PM4_CFG1 Q4[6:0]_CFG1

0x9E 7F

PM4_CFG2 Q4[6:0]_CFG2

0x9F 7F

PM4_CFG3 Q4[6:0]_CFG3

0xA0 7F

PM5_CFG0 Q5[6:0]_CFG0

0xA1 7F

PM5_CFG1 Q5[6:0]_CFG1

0xA2 7F

PM5_CFG2 Q5[6:0]_CFG2

0xA3 7F

PM5_CFG3 Q5[6:0]_CFG3

0xA4 7F

PM5_CFG4 Q5[6:0]_CFG4

0xA5 7F

PM5_CFG5 Q5[6:0]_CFG5

0xA6 7F

PM6_CFG4 Q6[6:0]_CFG4

0xA7 7F

PM6_CFG5 Q6[6:0]_CFG5

0xA8 7F

PM6_CFG0 Q6[6:0]_CFG0

0xA9 7F

PM6_CFG1 Q6[6:0]_CFG1

0xAA 7F

PM6_CFG2 Q6[6:0]_CFG2

0xAB 7F

PM6_CFG3 Q6[6:0]_CFG3

0xAC 00

TSSC[3:0]_CFG0 NSSC[3:0]_CFG0

PLL0 Spread Spectrum Control

0xAD 00

TSSC[3:0]_CFG1 NSSC[3:0]_CFG1

0xAE 00

TSSC[3:0]_CFG2 NSSC[3:0]_CFG2

0xAF 00

TSSC[3:0]_CFG3 NSSC[3:0]_CFG3

0xB0 00

TSSC[3:0]_CFG4 NSSC[3:0]_CFG4

0xB1 00

TSSC[3:0]_CFG5 NSSC[3:0]_CFG5

0xB2 00

DITH_CFG4 X2_CFG4 SSOFFSET[5:0]_CFG4

0xB3 00

DITH_CFG5 X2_CFG5 SSOFFSET[5:0]_CFG5

0xB4 00

DITH_CFG0 X2_CFG0 SSOFFSET[5:0]_CFG0

0xB5 00

DITH_CFG1 X2_CFG1 SSOFFSET[5:0]_CFG1

0xB6 00

DITH_CFG2 X2_CFG2 SSOFFSET[5:0]_CFG2

0xB7 00

DITH_CFG3 X2_CFG3 SSOFFSET[5:0]_CFG3

0xB8 11

SD1[3:0]_CFG0 SD0[3:0]_CFG0

0xB9 11

SD1[3:0]_CFG1 SD0[3:0]_CFG1

0xBA 11

SD1[3:0]_CFG2 SD0[3:0]_CFG2

Addr

Default

Hex

Value

Bit #

Description

7654321 0

IDT5V49EE901

EEPROM PROGRAMMABLE CLOCK GENERATOR CLOCK SYNTHESIZER

IDT®

EEPROM PROGRAMMABLE CLOCK GENERATOR 30

IDT5V49EE901 REV S 071015

. Memory bytes do not exist. Readback will be last value in shift register. If reading sequentially, value in 0x51 will be

returned.

0xBB 11

SD1[3:0]_CFG3 SD0[3:0]_CFG3

0xBC 11

SD1[3:0]_CFG4 SD0[3:0]_CFG4

0xBD 11

SD1[3:0]_CFG5 SD0[3:0]_CFG5

0xBE AE

SRC1[1:0]_CFG4 SRC0[1:0]_CFG4 PDPL3_CFG4 SM[1:0]_CFG4 PRIMSRC_CFG4

Output Divide Source Selection

0xBF AE

SRC1[1:0]_CFG5 SRC0[1:0]_CFG5 PDPL3_CFG5 SM[1:0]_CFG5 PRIMSRC_CFG5

PRIMSRC - primary source -

crystal or ICLOCK

0 = crystal/REFIN

1 = CLKIN

0xC0 AE

SRC1[1:0]_CFG0 SRC0[1:0]_CFG0 PDPL3_CFG0 SM[1:0]_CFG0 PRIMSRC_CFG0

SM = switch mode

0x = manual

10 = reserved

11 = auto-revertive

0xC1 AE

SRC1[1:0]_CFG1 SRC0[1:0]_CFG1 PDPL3_CFG1 SM[1:0]_CFG1 PRIMSRC_CFG1

PDPL3 - PLL3 shutdown

0 = normal

1 = shut down

0xC2 AE

SRC1[1:0]_CFG2 SRC0[1:0]_CFG2 PDPL3_CFG2 SM[1:0]_CFG2 PRIMSRC_CFG2

SRC = MUX control bit prior to

DIV#

SRC0[1:0]

00 - DIV1

01 - DIV3

10 - Reference input

0xC3 AE

SRC1[1:0]_CFG3 SRC0[1:0]_CFG3 PDPL3_CFG3 SM[1:0]_CFG3 PRIMSRC_CFG3

0xC4 24

SRC4[0]_CFG0 SRC3[2:0]_CFG0 SRC2[2:0]_CFG0 SRC1[2]_CFG0

SRC1/SRC2/SRC3..SRC5

000 - DIV1

001 - DIV3

010 - Reference input

011 - Reserved

100 - PLL0

101 - PLL1

110 - PLL2

111 - PLL3

0xC5 24

SRC4[0]_CFG1 SRC3[2:0]_CFG1 SRC2[2:0]_CFG1 SRC1[2]_CFG1

0xC6 24

SRC4[0]_CFG2 SRC3[2:0]_CFG2 SRC2[2:0]_CFG2 SRC1[2]_CFG2

0xC7 24

SRC4[0]_CFG3 SRC3[2:0]_CFG3 SRC2[2:0]_CFG3 SRC1[2]_CFG3

0xC8 24

SRC4[0]_CFG4 SRC3[2:0]_CFG4 SRC2[2:0]_CFG4 SRC1[2]_CFG4

0xC9 24

SRC4[0]_CFG5 SRC3[2:0]_CFG5 SRC2[2:0]_CFG5 SRC1[2]_CFG5

0xCA 49

SRC6[2:0]_CFG4 SRC5[2:0]_CFG4 SRC4[2:1]_CFG4

SRC6

000 - Reserved

001 - Reserved

010 - Reference input

011 - Reserved

100 - Reserved

101 - PLL1

110 - Reserved

111 - Reserved

Quiet MUX

0xCB 49

SRC6[2:0]_CFG5 SRC5[2:0]_CFG5 SRC4[2:1]_CFG5

0xCC 49

SRC6[2:0]_CFG0 SRC5[2:0]_CFG0 SRC4[2:1]_CFG0

0xCD 49

SRC6[2:0]_CFG1 SRC5[2:0]_CFG1 SRC4[2:1]_CFG1

0xCE 49

SRC6[2:0]_CFG2 SRC5[2:0]_CFG2 SRC4[2:1]_CFG2

0xCF 49

SRC6[2:0]_CFG3 SRC5[2:0]_CFG3 SRC4[2:1]_CFG3

Addr

Default

Hex

Value

Bit #

Description

7654321 0

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36

5V49EE901PGGI8

Mfr. #:

Buy 5V49EE901PGGI8

Manufacturer:

IDT

Description:

Clock Generators & Support Products EEPROM PROGRAMMABLE PLL

Lifecycle:

New from this manufacturer.

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5V49EE901PGGI8

5V49EE901PGGI8

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