OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

EVAL-ADV7842-7511P

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29
ADV7842
Rev. B | Page 18 of 28
Pin No. Mnemonic Type Description
M12 GND Ground Ground.
M13 GND Ground Ground.
M14 GND Ground Ground.
M15 GND Ground Ground.
M16 GND Ground Ground.
N1 LLC Digital video output Line-Locked Output Clock for the Pixel Data.
N2 P24 Digital video output Video Pixel Output Port.
N3 INT2 Miscellaneous digital
Interrupt. This pin can be active low or active high. When status bits change, this pin is
triggered. The events that trigger an interrupt are under user control.
N4 TEST4 Test Connect this pin to ground.
N5
RESET
Miscellaneous digital
System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required
to reset the ADV7842 circuitry.
N6 TEST6 Test Float this pin.
N7 SDRAM_A8 SDRAM interface Address Output. Interface to external RAM address lines.
N8 SDRAM_A4 SDRAM interface Address Output. Interface to external RAM address lines.
N9 SDRAM_A0 SDRAM interface Address Output. Interface to external RAM address lines.
N10
SDRAM_CS
SDRAM interface
Chip Select. SDRAM_CS enables and disables the command decoder on the RAM. One
of four command signals to the external SDRAM.
N11 SDRAM_LDQS SDRAM interface
Lower Data Strobe Pin. Data strobe pins are used for the RAM interface. This is an input
when reading data from external memory and an output when writing data to external
memory. It is edge aligned with data when reading from external memory and centered
with data when writing to external memory. SDRAM_LDQS corresponds to the data on
SDRAM_DQ7 to SDRAM_DQ0.
N12 SDRAM_DQ4 SDRAM interface Data Bus. Interface to external RAM 16-bit data bus.
N13 SDRAM_DQ15 SDRAM interface Data Bus. Interface to external RAM 16-bit data bus.
N14 SDRAM_DQ11 SDRAM interface Data Bus. Interface to external RAM 16-bit data bus.
N15 SDRAM_CK SDRAM interface
Differential Clock Output. All address and control output signals to the RAM should be
sampled on the positive edge of SDRAM_CK and on the negative edge of SDRAM_CK
.
N16 SDRAM_CKE SDRAM interface Clock Enable. This pin acts as an enable to the clock signals of the external RAM.
P1 P25 Digital video output Video Pixel Output Port.
P2 P26 Digital video output Video Pixel Output Port.
P3 TEST5 Test Connect this pin to ground.
P4 AVLINK Digital input/output Digital SCART Control Channel.
P5 TEST7 Test Float this pin.
P6 SDRAM_A11 SDRAM interface Address Output. Interface to external RAM address lines.
P7 SDRAM_A7 SDRAM interface Address Output. Interface to external RAM address lines.
P8 SDRAM_A3 SDRAM interface Address Output. Interface to external RAM address lines.
P9 SDRAM_A10 SDRAM interface Address Output. Interface to external RAM address lines.
P10
SDRAM_RAS
SDRAM interface
Row Address Select Command Signal. One of four command signals to the external
SDRAM.
P11 SDRAM_DQ7 SDRAM interface Data Bus. Interface to external RAM 16-bit data bus.
P12 SDRAM_DQ3 SDRAM interface Data Bus. Interface to external RAM 16-bit data bus.
P13 SDRAM_VREF SDRAM interface 1.25 V Reference for DDR SDRAM Interface or 1.65 V for SDR SDRAM Interface.
P14 SDRAM_DQ12 SDRAM interface Data Bus. Interface to external RAM 16-bit data bus.
P15 SDRAM_UDQS SDRAM interface
Upper Data Strobe Pin. Data strobe pins are used for the RAM interface. This is an input
when reading data from external memory and an output when writing data to external
memory. It is edge aligned with data when reading from external memory and centered
with data when writing to external memory. SDRAM_UDQS corresponds to the data
on SDRAM_DQ15 to SDRAM_DQ8.
P16
SDRAM_CK
SDRAM interface
Differential Clock Output. All address and control output signals to the RAM should be
sampled on the positive edge of SDRAM_CK and on the negative edge of SDRAM_CK
.
R1 P27 Digital video output Video Pixel Output Port.
R2 P28 Digital video output Video Pixel Output Port.
R3 P30 Digital video output Video Pixel Output Port.
R4 P32 Digital video output Video Pixel Output Port.
ADV7842
Rev. B | Page 19 of 28
Pin No. Mnemonic Type Description
R5 P34 Digital video output Video Pixel Output Port.
R6 SDRAM_A9 SDRAM interface Address Output. Interface to external RAM address lines.
R7 SDRAM_A6 SDRAM interface Address Output. Interface to external RAM address lines.
R8 SDRAM_A2 SDRAM interface Address Output. Interface to external RAM address lines.
R9 SDRAM_BA1 SDRAM interface Bank Address Output. Interface to external RAM bank address lines.
R10
SDRAM_CAS
SDRAM interface
Column Address Select Command Signal. One of four command signals to the
external SDRAM.
R11 SDRAM_DQ6 SDRAM interface Data Bus. Interface to external RAM 16-bit data bus.
R12 SDRAM_DQ2 SDRAM interface Data Bus. Interface to external RAM 16-bit data bus.
R13 SDRAM_DQ0 SDRAM interface Data Bus. Interface to external RAM 16-bit data bus.
R14 SDRAM_DQ13 SDRAM interface Data Bus. Interface to external RAM 16-bit data bus.
R15 SDRAM_DQ9 SDRAM interface Data Bus. Interface to external RAM 16-bit data bus.
R16 SDRAM_DQ8 SDRAM interface Data Bus. Interface to external RAM 16-bit data bus.
T1 GND Ground Ground.
T2 P29 Digital video output Video Pixel Output Port.
T3 P31 Digital video output Video Pixel Output Port.
T4 P33 Digital video output Video Pixel Output Port.
T5 P35 Digital video output Video Pixel Output Port.
T6 GND Ground Ground.
T7 SDRAM_A5 SDRAM interface Address Output. Interface to external RAM address lines.
T8 SDRAM_A1 SDRAM interface Address Output. Interface to external RAM address lines.
T9 SDRAM_BA0 SDRAM interface Bank Address Output. Interface to external RAM bank address lines.
T10
SDRAM_WE
SDRAM interface
Write Enable Output Command Signal. One of four command signals to the external
SDRAM.
T11 SDRAM_DQ5 SDRAM interface Data Bus. Interface to external RAM 16-bit data bus.
T12 GND Ground Ground.
T13 SDRAM_DQ1 SDRAM interface Data Bus. Interface to external RAM 16-bit data bus.
T14 SDRAM_DQ14 SDRAM interface Data Bus. Interface to external RAM 16-bit data bus.
T15 SDRAM_DQ10 SDRAM interface Data Bus. Interface to external RAM 16-bit data bus.
T16 GND Ground Ground.
ADV7842
Rev. B | Page 20 of 28
FUNCTIONAL OVERVIEW
HDMI RECEIVER
The ADV7842 front end incorporates a 2:1 multiplexed HDMI
1.4 receiver with Xpressview fast switching technology and
support for HDMI 1.4 features such as 3D TV. Building on the
feature set of Analog Device existing HDMI devices, the ADV7842
also offers support for all HD TV formats up to 12-bit, 1080p
Deep Color and all display resolutions up to UXGA (1600 ×
1200 at 60 Hz). Xpressview fast switching technology, using
Analog Devices hardware-based HDCP engine that minimizes
software overhead, allows switching between the two input
ports in less than 1 second.
With the inclusion of HDCP 1.4, the ADV7842 can receive
encrypted video content. The HDMI interface of the ADV7842
allows for authentication of a video receiver, decryption of
encoded data at the receiver, and renewal of that authentication
during transmission, as specified by the HDCP 1.4 protocol.
Repeater support is also offered by the ADV7842.
The HDMI receiver incorporates active equalization of the
HDMI data signals. This equalization compensates for the high
frequency losses inherent in HDMI and DVI cabling, especially
at longer lengths and higher frequencies. It is capable of
equalizing for cable lengths up to 30 meters to achieve robust
receiver performance at even the highest HDMI data rates.
The HDMI receiver offers advanced audio functionality. It
supports multichannel I
2
S audio for up to eight channels. It also
supports a 6-DSD channel interface with each channel carrying
an over-sampled 1-bit representation of the audio signal as
delivered on SACD. The ADV7842 can also receive HBR audio
packet streams and outputs them through the HBR interface in
an SPDIF format conforming to the IEC60958 standard.
The receiver contains an audio mute controller that can detect a
variety of conditions that may result in audible extraneous noise
in the audio output. On detection of these conditions, the audio
signal can be ramped to mute to prevent audio clicks or pops.
HDMI receiver features include:
• 2:1 multiplexed HDMI receiver
• HDMI 1.4, 3D format support, DVI 1.0
• 225 MHz HDMI receiver
• Integrated equalizer
• High-bandwidth Digital Content Protection (HDCP 1.4)
also on background ports
• Internal HDCP keys
• 36-/30-bit Deep Color support
• PCM, HBR, DSD audio packet support
• Repeater support
• Internal E-EDID RAM
• Hot plug assert output pin for each HDMI port
• CEC controller
ANALOG FRONT END
The ADV7842 analog front end comprises four 170 MHz, 12-bit
ADCs that digitize the analog video signal before applying it to
the standard definition processor (SDP) or component
processor (CP). The analog front end uses differential channels
to each ADC to ensure high performance in a mixed-signal
application. The front end also includes a 12-channel input mux
that enables multiple video signals to be applied to the
ADV7842 without the requirement of an external mux.
Current and voltage clamp control loops ensure that any DC
offsets are removed from the video signal. The clamps are
positioned in front of each ADC to ensure that the video signal
remains within the range of the converter.
The ADCs are configured to run up to 8× oversampling mode
when decoding composite or S-Video inputs. For component
525i, 625i, 525p, and 625p sources, 4× oversampling is performed.
All other video standards are 1× oversampled. Oversampling
the video signals reduces the cost and complexity of external
antialiasing filters with the benefit of an increased signal-to-
noise ratio (SNR).
Optional internal antialiasing filters with programmable
bandwidth are positioned in front of each ADC. These filters
can be used to band limit video signals, removing spurious, out-
of-band noise.
The ADV7842 can support the simultaneous processing of
CVBS and RGB standard definition signals to enable SCART
compatibility and overlay functionality. A combination of
CVBS and RGB inputs can be mixed with the output under the
control of I
2
C registers.
Analog front-end features include:
• Four 170 MHz, NSV, 12-bit ADCs that enable true 12-bit
video decoding
• 12-channel analog input mux that enables multiple source
connections without the requirement of an external mux
• Four current and voltage clamp control loops that ensure
any dc offsets are removed from the video signal
• SCART functionality and SD RGB overlay on CVBS
controlled by fast blank input
• SCART source switching detection through TRI1-TRI8 input
• Four programmable antialiasing filters
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P29

EVAL-ADV7842-7511P

Mfr. #:
Buy EVAL-ADV7842-7511P
Manufacturer:
Analog Devices Inc.
Description:
Video IC Development Tools Require HDMI license see product comment
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet