LTC6403-1
17
64031fa
APPLICATIONS INFORMATION
resistor values (but still less than 2k) will result in higher
output noise, but improved distortion due to less loading
on the output. The optimal feedback resistance for the
LTC6403-1 runs between 400Ω to 2k.
The differential fi ltered outputs +OUTF and –OUTF will have
a little higher spot noise than the unfi ltered outputs (due
to the two 100Ω resistors which contribute 1.3nV/√Hz
each), but actually will provide superior signal-to-noise
ratios in noise bandwidths exceeding 69.4Mhz due to the
noise-fi ltering function the fi lter provides.
Layout Considerations
Because the LTC6403-1 is a very high speed amplifi er, it is
sensitive to both stray capacitance and stray inductance.
Three pairs of power supply pins are provided to keep the
power supply inductance as low as possible to prevent
any degradation of amplifi er 2nd Harmonic distortion
performance. It is critical that close attention be paid to
supply bypassing. For single supply applications (Pins
3, 9 and 12 grounded) it is recommended that 3 high
quality 0.1μF surface mount ceramic bypass capacitor be
placed between pins 2 and 3, between pins 11and 12, and
between pins10 and 9 with direct short connections. Pins
3, 9 and 10 should be tied directly to a low impedance
ground plane with minimal routing. For dual (split) power
supplies, it is recommended that at least two additional
high quality, 0.1μF ceramic capacitors are used to bypass
pin V
+
to ground and V
–
to ground, again with minimal
routing. For driving large loads (<200Ω), additional bypass
capacitance may be needed for optimal performance. Keep
in mind that small geometry (e.g. 0603) surface mount
ceramic capacitors have a much higher self resonant
frequency than do leaded capacitors, and perform best
in high speed applications.
Any stray parasitic capacitances to ground at the sum-
ming junctions +IN, and –IN should be kept to an absolute
minimum even if it means stripping back the ground plane
away from any trace attached to this node. This becomes
especially true when the feedback resistor network uses
resistor values >2k in circuits with R
F
= R
I
. Excessive
peaking in the frequency response can be mitigated by
adding small amounts of feedback capacitance around
R
F
. Always keep in mind the differential nature of the
LTC6403-1, and that it is critical that the load impedances
seen by both outputs (stray or intended) should be as bal-
anced and symmetric as possible. This will help preserve
the natural balance of the LTC6403-1, which minimizes the
generation of even order harmonics, and preserves the
rejection of common mode signals and noise.
It is highly recommended that the V
OCM
pin be either hard
tied to a low impedance ground plane (in split supply
applications), or bypassed to ground with a high quality
ceramic capacitor whose value exceeds 0.01μF. This will
help stabilize the common mode feedback loop as well as
prevent thermal noise from the internal voltage divider and
other external sources of noise from being converted to
differential noise due to divider mismatches in the feed-
back networks. It is also recommended that the resistive
feedback networks comprise 1% resistors (or better) to
enhance the output common mode rejection. This will also
prevent the V
OCM
-referred common mode noise of the
common mode amplifi er path (which cannot be fi ltered)
from being converted to differential noise, degrading the
differential noise performance.
Figure 10. LTC6403-1 Output Spot Noise vs Spot Noise
Contributed by Feedback Network Alone
R
F
= R
I
(Ω)
100
1
nV/√Hz
10
100
1k 10k
64031 F10
FEEDBACK RESISTOR
NETWORK NOISE ALONE
TOTAL (AMPLIFIER AND
FEEDBACK NETWORK)
OUTPUT NOISE
