LTC6403-1
5
64031fa
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The inputs +IN, –IN are protected by a pair of back-to-back diodes.
If the differential input voltage exceeds 1.4V, the input current should be
limited to less than 10mA. Input pins (+IN, –IN, V
OCM
, and SHDN) are also
protected by steering diodes to either supply. If the inputs should exceed
either supply voltage, the input current should be limited to less than
10mA.
Note 3: A heat sink may be required to keep the junction temperature
below the absolute maximum rating when the output is shorted
indefi nitely. Long term application of output currents in excess of the
absolute maximum ratings may impair the life of the device.
Note 4: The LTC6403-1 is guaranteed functional over the operating
temperature range –40°C to 85°C.
Note 5: The LTC6403C-1 is guaranteed to meet specifi ed performance
from 0°C to 70°C. The LTC6403C-1 is designed, characterized, and
expected to meet specifi ed performance from –40°C to 85°C but is
not tested or QA sampled at these temperatures. The LTC6403I-1 is
guaranteed to meet specifi ed performance from –40°C to 85°C.
Note 6: Input bias current is defi ned as the average of the input currents
fl owing into Pin 6 and Pin 15 (–IN, and +IN). Input offset current is defi ned
as the difference of the input currents fl owing into Pin 15 and Pin 6 (I
OS
=
I
B
+
– I
B
–
)
Note 7: Input common mode range is tested using the test circuit of
Figure 1 by measuring the differential gain with a ±1V differential output
with V
ICM
= mid-supply, and also with V
ICM
at the input common mode
range limits listed in the Electrical Characteristics table, verifying that the
differential gain has not deviated from the mid supply common mode input
case by more than 1%, and the common mode offset (V
OSCM
) has not
deviated from the mid-supply case by more than ±10mV.
The voltage range for the output common mode range is tested using the
test circuit of Figure 1 by applying a voltage on the V
OCM
pin and testing at
both mid supply and at the Electrical Characteristics table limits to verify
that the differential gain has not deviated from the mid supply V
OCM
case
by more than 1%, and the common mode offset (V
OSCM
) has not deviated
by more than ±10mV from the mid supply case.
Note 8: Input CMRR is defi ned as the ratio of the change in the input
common mode voltage at the pins +IN or –IN to the change in differential
input referred voltage offset. Output CMRR is defi ned as the ratio of the
change in the voltage at the V
OCM
pin to the change in differential input
referred voltage offset. These specifi cations are strongly dependent on
feedback ratio matching between the two outputs and their respective
inputs, and it is diffi cult to measure actual amplifi er performance. See The
Effects of Resistor Pair Mismatch in the Applications Information section
of this datasheet. For a better indicator of actual amplifi er performance
independent of feedback component matching, refer to the PSRR
specifi cation.
Note 9: Differential power supply rejection (PSRR) is defi ned as the ratio
of the change in supply voltage to the change in differential input referred
voltage offset. Common mode power supply rejection (PSRRCM) is
defi ned as the ratio of the change in supply voltage to the change in the
common mode offset, V
OUTCM
– V
OCM
.
Note 10: Output swings are measured as differences between the output
and the respective power supply rail.
Note 11: Extended operation with the output shorted may cause junction
temperatures to exceed the 150°C limit and is not recommended. See Note
3 for more details.
Note 12: A resistive load is not required when driving an AD converter with
the LTC6403-1. Therefore, typical output power is very small. In order to
compare the LTC6403-1 with amplifi ers that require 50Ω output load, the
LTC6403-1 output voltage swing driving a given R
L
is converted to OIP3 as
if it were driving a 50Ω load. Using this modifi ed convention, 2V
P-P
is by
defi nition equal to 10dBm, regardless of actual R
L
.
The l denotes the specifi cations which apply
over the full operating temperature range, otherwise specifi cations are at T
A
= 25°C, V
+
= 3V, V
–
= 0V, V
CM
= V
OCM
= V
ICM
= Mid-Supply,
V
SHDN
= OPEN, R
I
= 402Ω, R
F
= 402Ω, R
T
= 25.5Ω, unless otherwise noted (See Figure 2). V
S
is defi ned (V
+
– V
–
). V
OUTCM
is defi ned
as (V
+OUT
+ V
–OUT
)/2. V
ICM
is defi ned as (V
+IN
+ V
–IN
)/2. V
OUTDIFF
is defi ned as (V
+OUT
– V
–OUT
). V
INDIFF
is defi ned as (V
INP
– V
INM
).
LTC6403-1 AC ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
IMD Third-Order IMD at 10MHz
f1 = 9.5MHz, f2 = 10.5MHz
V
S
= 3V, V
OUTDIFF
= 2V
P-P
Envelope –72 dBc
OIP3 Equivalent OIP3 at 3MHz (Note 12) V
S
= 3V 48 dBm
t
S
Settling Time
2V Step at Output
V
S
= 3V, Single-Ended Input
1% Settling
0.1% Settling
20
30
ns
ns
NF Noise Figure, f = 3MHz
R
SOURCE
= 804Ω, R
I
= 402Ω,
R
F
= 402Ω, V
S
= 3V
R
SOURCE
= 200Ω, R
I
= 100Ω,
R
F
= 402Ω, V
S
= 3V
10.8
8.9
dB
dB
f
3dBFILTER
Differential Filter 3dB Bandwidth 44.2 MHz
