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9FGP202AKLFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
9FGP202A
FREQUENCY TIMING GENERATOR FOR PERIPHERALS
IDT®
FREQUENCY TIMING GENERATOR FOR PERIPHERALS 10
9FGP202A REV D 070511
Electrical Characteristics–RMII - 50MHz
Electrical Characteristics–33.33MHz
PARAMETER SYMBOL CONDITIONS* MIN TYP MAX UNITS NOTES
Long Accuracy ppm see Tperiod min-max values -50 0 50 ppm 1,2
Clock period Tperiod 50.00MHz output nominal 19.990 20.000 20.010 ns 1
Output High Voltage
V
OH
I
OH
= -1 mA
2.4 V 1
Output Low Voltage
V
OL
I
OL
= 1 mA
0.4 V 1
V
OH
@MIN = 1.0 V -33 mA 1
V
OH
@MAX = 3.135 V -33 mA 1
V
OL
@ MIN = 1.95 V 30 mA 1
V
OL
@ MAX = 0.4 V
38 mA 1
Rise Time t
r
V
OL
= 0.4 V, V
OH
= 2.4 V 1 3 ns
1
Fall Time t
f
V
OH
= 2.4 V , V
OL
= 0.4 V 1 3 ns 1
Dut y C ycle d
t1
V
T
= 1.5 V 35 65 % 1
t
skew _3 V50(3 :0)
t
skew _3 V50(7 :4)
Jitter, Long Term t
jabs
V
T
= 1.5 V, 10
∪
sec interval 500 ps 1
Ji tt er, Peak
t
jpe ak
V
T
= 1.5 V
100 ps 1,3
*TA = 0 - 70°C; S upply Voltage VDD = 3.3 V +/-5%, CL = 5 pF with Rs as shown in the termination table (unless otherwise specified)
1
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 25.00MHz
3
1/2 of the peak-to-peak jitte r. (Lg+ + |Lg-|)/2
200 ps 1Group Skew
V
T
= 1.5 V,
for each group of 4 outputs
Output High Current I
OH
Output Low Current I
OL
PARAMETER SYMB OL CONDITIONS* MIN TYP MAX UNITS NOTES
Long Accuracy ppm see Tperiod min-max values -100 0 100 ppm 1
Clock period Tperiod 33.33MHz output non-spread 29.970 30.000 30.030 ns 1
Absolute min/max period Tabs 33.33MHz output non-spread 29.720
30.000 30.280
ns
1
Output High Voltage
V
OH
I
OH
= -1 mA
2.4 V 1
Output Low Voltage
V
OL
I
OL
= 1 mA
0.4 V 1
V
OH
@MIN = 1.0 V -33 mA 1
V
OH
@MAX = 3.135 V -33 mA 1
V
OL
@ MIN = 1.95 V 30 mA 1
V
OL
@ MAX = 0.4 V
38 mA 1
Rise Time t
r
V
OL
= 0.4 V , V
OH
= 2.4 V 0.5 2 ns
1
Fall Time t
f
V
OH
= 2.4 V , V
OL
= 0.4 V 0.5 2 ns 1
Dut y C ycle d
t1
V
T
= 1.5 V 45 55 % 1
Jitt er, Cyc le to cycle
t
jcyc -cyc
V
T
= 1.5 V
250 ps 1
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5 pF with Rs as shown in the termination table (unless otherwise specified)
1
Guaranteed by design and characterization, not 100% tested in production.
Output High Current I
OH
Output Low Current I
OL
9FGP202A
FREQUENCY TIMING GENERATOR FOR PERIPHERALS
IDT®
FREQUENCY TIMING GENERATOR FOR PERIPHERALS 11
9FGP202A REV D 070511
Electrical Characteristics–32.768kHz
Electrical Characteristics–REF - 25MHz
PARAMETER SYMBOL CONDITIONS* MIN TYP MAX UNITS NOTES
Long Accuracy ppm see Tperiod min-max values -100 100 ppm 1
Clock period Tperiod 32.768KHz output nominal 30.518 us 1
Output High Voltage
V
OH
I
OH
= -1 mA
2.4 V 1
Output Low Voltage
V
OL
I
OL
= 1 mA
0.4 V 1
V
OH
@MIN = 1.0 V -33 mA 1
V
OH
@MAX = 3.135 V -33 mA 1
V
OL
@ MIN = 1.95 V 30 mA 1
V
OL
@ MAX = 0.4 V
38 mA 1
Rise Time t
r
V
OL
= 0.4 V, V
OH
= 2.4 V 1 4 ns
1
Fall Time t
f
V
OH
= 2.4 V , V
OL
= 0.4 V 1 4 ns 1
Dut y C ycle d
t1
V
T
= 1.5 V 45 55 % 1
Jitt er, Cyc le to cycle
t
jcyc -cyc
V
T
= 1.5 V
500 ps 1
*TA = 0 - 70°C; S upply Voltage VDD = 3.3 V +/-5%, CL = 5 pF with Rs as shown i n the termination table (unless otherwise specified)
1
Guaranteed by design and characterization, not 100% tested in production.
Output High Current I
OH
Output Low Current I
OL
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Notes
Long Accuracy ppm see Tperiod min-max values -50 50 ppm 1,2
Clock period T
pe rio d
25.00MHz output nominal 39.980 40.000 40.020 ns 2
Outp ut High Volta ge
V
OH
I
OH
= -1 mA
2.4 V 1
Output Low Voltage
V
OL
I
OL
= 1 mA
0.4 V 1
V
OH
@MIN = 1.0 V -29 mA 1
V
OH
@MAX = 3.135 V -23 mA 1
V
OL
@ MIN = 1.95 V
29 mA 1
V
OL
@ MAX = 0.4 V
27 mA 1
Rise Time t
r1
V
OL
= 0.4 V, V
OH
= 2.4 V 1 2 ns 1
Fall Time t
f1
V
OH
= 2.4 V, V
OL
= 0.4 V 1 2 ns 1
Skew t
sk1
V
T
= 1.5 V 500 ps 1
Duty Cycle
d
t1
V
T
= 1.5 V
45 55 % 1
Ji tter
t
jcyc -cyc
V
T
= 1.5 V
500 ps 1
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 5 pF with Rs as shown i n the termination table (unless otherwise specified)
1
Guaranteed b
y
desi
g
n and characterization, not 100% tested in
p
roduction.
2
All Lon
g
Term Accurac
y
and Clock Period s
p
ecifications are
g
uaranteed assumin
g
that REFOUT is at 25.000MHz
I
OL
Output Low Current
I
OH
Output High Current
9FGP202A
FREQUENCY TIMING GENERATOR FOR PERIPHERALS
IDT®
FREQUENCY TIMING GENERATOR FOR PERIPHERALS 12
9FGP202A REV D 070511
General SMBus Serial Interface Information
How to Write
• Controller (host) sends a start bit
• Controller (host) sends the write address
• IDT clock will acknowledge
• Controller (host) sends the beginning byte location = N
• IDT clock will acknowledge
• Controller (host) sends the byte count = X
• IDT clock will acknowledge
• Controller (host) starts sending Byte N through Byte
N+X-1
• IDT clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
* By default, SMBADR = 0,
therefore, SMBus WRITE/READ address is D0/D1.
Please see SMBus Address Selection table on page 2.
How to Read
• Controller (host) will send a start bit
• Controller (host) sends the write address
• IDT clock will acknowledge
• Controller (host) sends the beginning byte location = N
• IDT clock will acknowledge
• Controller (host) will send a separate start bit
• Controller (host) sends the read address
• IDT clock will acknowledge
• IDT clock will send the data byte count = X
• IDT clock sends Byte N+X-1
• IDT clock sends Byte 0 through Byte X (if X
(H)
was
written to Byte 8)
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) IDT (Slave/Receiver)
TstarT bit
Slave Address
WR WRite
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
X Byte
ACK
O
O O
O O
O
Byte N + X - 1
ACK
PstoP bit
Read Address Write Address
*D1
(H)
*D0
(H)
Index Block Read Operation
Controller (Host) IDT (Slave/Receiver)
TstarT bit
Slave Address
WR WRite
ACK
Beginning Byte = N
ACK
RT Repeat starT
Slave Address
RD ReaD
ACK
Data Byte Count=X
ACK
X Byte
Beginning Byte N
ACK
O
O O
O O
O
Byte N + X - 1
N Not acknowledge
PstoP bit
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

9FGP202AKLFT

Mfr. #:
Buy 9FGP202AKLFT
Manufacturer:
IDT
Description:
Clock Generators & Support Products CK-MNG SERVER PERIPH ERAL CLOCK
Lifecycle:
New from this manufacturer.
Delivery:
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