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9FGP202AKLFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
9FGP202A
FREQUENCY TIMING GENERATOR FOR PERIPHERALS
IDT®
FREQUENCY TIMING GENERATOR FOR PERIPHERALS 13
9FGP202A REV D 070511
SMBus Table: CPU Frequency Select and Spread Spectrum Control Register
Byte 0 Name Control Function Type 0 1 PWD
Bit 7
Reserved Reserved RW 0
Bit 6
Reserved Reserved Rev 0.20 0
Bit 5
Reserved Reserved RW 0
Bit 4
DOT96 SS_EN DOT96 Spread Spectrum Enable RW Disable Enable 0
Bit 3
CPU SS_EN CPU Spread Spectrum Enable RW 0
Bit 2
CPU FS2 CPU Freq Select Bit 2 RW 0
Bit 1
CPU FS1 CPU Freq Select Bit 1 RW 1
Bit 0
CPU FS0 CPU Freq Select Bit 0 RW 0
SMBus Table: RMII Output Control R egister
Byte 1 Name Control Function Type 0 1 PWD
Bit 7
RMII_7 Enable RMII_7 Output Control RW Disable Enable 1
Bit 6
RMII_6 Enable RMII_6 Out
p
ut Control RW Disable Enable 1
Bit 5
RMII_5 Enable RMII_5 Out
p
ut Control RW Disable Enable 1
Bit 4
RMII_4 Enable RMII_4 Out
p
ut Control RW Disable Enable 1
Bit 3
RMII_3 Enable RMII_3 Out
p
ut Control RW Disable Enable 1
Bit 2
RMII_2 Enable RMII_2 Out
p
ut Control RW Disable Enable 1
Bit 1
RMII_1 Enable RMII_1 Out
p
ut Control RW Disable Enable 1
Bit 0
RMII_0 Enable RMII_0 Output Control RW Disable Enable 1
SMBus Table: DOT, CPU, 32.768KHz, 25MHz and 33.33MHz Outputs Control Register
Byte 2 Name Control Function Type 0 1 PWD
Bit 7
CPUCLK PD Drive Mode Driven in PD RW Driven Hi-Z 0
Bit 6
DOT96SS PD Drive Mode Driven in PD RW Driven Hi-Z 0
Bit 5
33.33MHz Enable 33.33MHz Output Control RW Disable Enable 1
Bit 4
25MHz_1 Enable 25MHz_1 Output Control RW Disable Enable 1
Bit 3
25MHz_0 Enable 25MHz_0 Output Control RW Disable Enable 1
Bit 2
32.768kHz Enable 32.768KHz Output Control RW Disable Enable 1
Bit 1
CPUCLK Enable CPUCLK Output Control RW Disable Enable 1
Bit 0
DOT96SS Enable D OT96SS Output Control RW Disable Enable 1
SMBus Table: DOT96 Frequency Select and Spread Spectrum Control Register
Byte 3 Name Control Function Type 0 1 PWD
Bit 7
Reserved Reserved RW 0
Bit 6
Reserved Reserved RW 0
Bit 5
Reserved Reserved RW 0
Bit 4
Reserved Reserved RW 0
Bit 3
DOT96SS FS3 DOT96 Freq Select Bit 3 RW 0
Bit 2
DOT96SS FS2 DOT96 Freq Select Bit 2 RW 0
Bit 1
DOT96SS FS1 DOT96 Fre
q
Select Bit 1 RW 0
Bit 0
DOT96SS FS0 DOT96 Freq Select Bit 0 RW 0
SMBus Table: RMII Strength Control Register
Byte 4 Name Control Function Type 0 1 PWD
Bit 7
RMII_7 Str RMII_7 Strength Co ntrol RW 1-Load (1X) 2-Loads (2X) 0
Bit 6
RMII_6 Str RMII_6 Strength Co ntrol RW 1-Load (1X) 2-Loads (2X) 0
Bit 5
RMII_5 Str RMII_5 Strength Co ntrol RW 1-Load (1X) 2-Loads (2X) 0
Bit 4
RMII_4 Str RMII_4 Strength Co ntrol RW 1-Load (1X) 2-Loads (2X) 0
Bit 3
RMII_3 Str RMII_3 Strength Co ntrol RW 1-Load (1X) 2-Loads (2X) 0
Bit 2
RMII_2 Str RMII_2 Strength Co ntrol RW 1-Load (1X) 2-Loads (2X) 0
Bit 1
RMII_1 Str RMII_1 Strength Co ntrol RW 1-Load (1X) 2-Loads (2X) 0
Bit 0
RMII_0 Str RMII_0 Strength Co ntrol RW 1-Load (1X) 2-Loads (2X) 0
SMBus Table: 32.768KHz, 25Mhz and 33.33MHz Strength Control Registe
r
Byte 5 Name Control Function Type 0 1 PWD
Bit 7
Reserved Reserved RW Reserved 0
Bit 6
Reserved Reserved RW Reserved 0
Bit 5
33.33MHz Str 33 .33MH z Stren
g
th Control RW 1-Load
(
1X
)
2-Load s
(
2X
)
1
Bit 4
25MHz_1 St
r
25MHz_1 Stren
g
th Control RW 1-Load
(
1X
)
2-Load s
(
2X
)
1
Bit 3
25MHz_0 St
r
25MHz_1 Stren
g
th Control RW 1-Load
(
1X
)
2-Load s
(
2X
)
1
Bit 2
32.768kHz Str 32.768kHz Stren
g
th Control RW 1-Load
(
1X
)
2-Load s
(
2X
)
1
Bit 1
Reserved Reserved RW Reserved 0
Bit 0
Reserved Reserved RW Reserved 0
25
-
-
37
7,8
-
3,4
22
17
-
-
-
Pin #
28
29
32
33
16
- Reserved
-
Reserved
Reserved
-
-
24
36
-
-
-
13
-
6
5
-
-
32
29
28
25
Reserved
Reserved
See Table 2:
DOT Frequency Selection Table
33
Reserved
See Table 1:
CPU Frequency Selection Table
-
-
22
17
16
13
-
-
24
Pin #
Reserved
Pin #
Pin #
Pin #
Pin #
37
36
9FGP202A
FREQUENCY TIMING GENERATOR FOR PERIPHERALS
IDT®
FREQUENCY TIMING GENERATOR FOR PERIPHERALS 14
9FGP202A REV D 070511
SMBus Table: Vendor & Revision ID Register
Byte 6 Name Control Function Type 0 1 PWD
Bit 7
RID3 R - - X
Bit 6
RID2 R - - X
Bit 5
RID1 R - - X
Bit 4
RID0 R - - X
Bit 3
VID3 R - - 0
Bit 2
VID2 R - - 0
Bit 1
VID1 R - - 0
Bit 0
VID0 R - - 1
SMBus Table: Device ID
Byte 7 Name Control Function Type 0 1 PWD
Bit 7
Device ID 7 (MSB) RW 0
Bit 6
Device ID 6 RW 0
Bit 5
Device ID 5 RW 1
Bit 4
Device ID 4 RW 0
Bit 3
Device ID 3 RW 0
Bit 2
Device ID 2 RW 0
Bit 1
Device ID 1 RW 1
Bit 0
Device ID 0 (LSB) RW 0
SMBus Table: Byte Count Register
Byte 8 Name Control Function Type 0 1 PWD
Bit 7
BC7 RW - - 0
Bit 6
BC6 RW - - 0
Bit 5
BC5 RW - - 0
Bit 4
BC4 RW - - 0
Bit 3
BC3 RW - - 1
Bit 2
BC2 RW - - 0
Bit 1
BC1 RW - - 0
Bit 0
BC0 RW - - 1
SMBus Table: Reserved
Byte 9 Name Control Function Type 0 1 PWD
Bit 7
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
SMBus Table: PLLs M/N Programming Enable Register
Byte 10 Name Control Function Type 0 1 PWD
Bit 7
M/N_EN PLLs M/N Programming Enable RW Disable Enable 0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0
0
SMBus Table: CPU PLL VCO Frequency Control Register
Byte 11 Name Control Function Type 0 1 PWD
Bit 7
N Div8 N Divider Pro
g
bit 8 RW
X
Bit 6
N Div 9 N Divider Pro
g
bit 9 RW
X
Bit 5
M Div5 RW
X
Bit 4
M Div4 RW
X
Bit 3
M Div3 RW
X
Bit 2
M Div2 RW
X
Bit 1
M Div1 RW
X
Bit 0
M Div0 RW X
Reserved
Reserved
M Divider Programming bits
-
-
-
Pin #
-
Pin #
-
Pin #
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
The decimal representation of M and N
Divier in Byte 11 and 12 will configure
the VCO frequency. Default at power up
= latch-in or Byte 0 Rom table. VCO
Frequency = 14.318 x [NDiv(9:0)+8] /
[MDiv(5:0)+2]
Reserved
Reserved
-
-
-
-
-
-
-
-
REVISION ID
-
-
VENDOR ID
-
-
-
-
-
Pin #
-
-
-
-
-
-
Reserved
Reserved
-
Writing to this register configures how
many bytes will be read back.
-
-
-
-
-
-
Pin #
Device ID
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Pin #
9FGP202A
FREQUENCY TIMING GENERATOR FOR PERIPHERALS
IDT®
FREQUENCY TIMING GENERATOR FOR PERIPHERALS 15
9FGP202A REV D 070511
SMBus Table: CPU PLL VCO Frequency Control Register
Byte 12 Name Control Function Type 0 1 PWD
Bit 7
N Div7 RW X
Bit 6
N Div6 RW X
Bit 5
N Div5 RW X
Bit 4
N Div4 RW X
Bit 3
N Div3 RW X
Bit 2
N Div2 RW X
Bit 1
N Div1 RW X
Bit 0
N Div0 RW X
SMBus Table: CPU PLL Spread Spectrum C ontrol Register
Byte 13 Name Control Function Type 0 1 PWD
Bit 7
SSP7 RW X
Bit 6
SSP6 RW X
Bit 5
SSP5 RW X
Bit 4
SSP4 RW X
Bit 3
SSP3 RW X
Bit 2
SSP2 RW X
Bit 1
SSP1 RW X
Bit 0
SSP0 RW X
SMBus Table: CPU PLL Spread Spectrum C ontrol Register
Byte 14 Name Control Function Type 0 1 PWD
Bit 7
0
Bit 6
SSP14 RW
X
Bit 5
SSP13 RW
X
Bit 4
SSP12 RW
X
Bit 3
SSP11 RW
X
Bit 2
SSP10 RW
X
Bit 1
SSP9 RW
X
Bit 0
SSP8 RW X
SMBus Table: DOT PLL VCO Frequency Control Register
Byte 15 Name Control Function Type 0 1 PWD
Bit 7
N Div8 N Divider Prog bit 8 RW X
Bit 6
N Div9 N Divider Prog bit 9 RW X
Bit 5
M Div5 RW X
Bit 4
M Div4 RW X
Bit 3
M Div3 RW X
Bit 2
M Div2 RW X
Bit 1
M Div1 RW X
Bit 0
M Div0 RW X
SMBus Table: DOT PLL VCO Frequency Control Register
Byte 16 Name Control Function Type 0 1 PWD
Bit 7
N Div7 RW X
Bit 6
N Div6 RW X
Bit 5
N Div5 RW X
Bit 4
N Div4 RW X
Bit 3
N Div3 RW X
Bit 2
N Div2 RW X
Bit 1
N Div1 RW X
Bit 0
N Div0 RW X
SMBus Table: DOT PLL Spread Spectrum Control Register
Byte 17 Name Control Function Type 0 1 PWD
Bit 7
SSP7 RW
X
Bit 6
SSP6 RW
X
Bit 5
SSP5 RW
X
Bit 4
SSP4 RW
X
Bit 3
SSP3 RW
X
Bit 2
SSP2 RW
X
Bit 1
SSP1 RW
X
Bit 0
SSP0 RW X
These Spread Spectrum bits in Byte 13
and 14 will program the spread
pecentage. It is recommended to use
ICS Sprea d % table for spread
programming.
Reserved
M Divider Programming bits
-
-
Pin #
-
-
-
-
-
-
-
-
Pin #
-
-
Spread Spectrum Program ming
b(7:0)
These Spread Spectrum bits in Byte 19
and 20 will program the spread
pecentage. It is recommended to use
ICS Sprea d % table for spread
programming.
-
-
-
-
-
-
-
-
Pin #
-
-
-
-
-
-
-
-
-
Spread Spectrum Program ming
b(7:0)
-
Spread Spectrum Program ming
b(14:8)
-
Pin #
-
-
-
-
-
These Spread Spectrum bits in Byte 13
and 14 will program the spread
pecentage. It is recommended to use
ICS Sprea d % table for spread
programming.
-
-
-
-
-
Pin #
The decimal representation of M and N
Divier in Byte 17 and 18 will configure
the VCO frequency. Default at power up
= Byte 0 Rom table. VCO Frequency =
14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2]
N Divider Programming b(7:0)
The decimal representation of M and N
Divier in Byte 17 and 18 will configure
the VCO frequency. Default at power up
= Byte 0 Rom table. VCO Frequency =
14.318 x [NDiv(9:0)+8] / [MDiv(5:0)+2]
-
-
-
-
-
N Divider Programming b(7:0)
The decimal representation of M and N
Divier in Byte 11 and 12 will configure
the VCO frequency. Default at power up
= latch-in or Byte 0 Rom table. VCO
Frequency = 14.318 x [NDiv(9:0)+8] /
[MDiv(5:0)+2]
Pin #
-
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

9FGP202AKLFT

Mfr. #:
Buy 9FGP202AKLFT
Manufacturer:
IDT
Description:
Clock Generators & Support Products CK-MNG SERVER PERIPH ERAL CLOCK
Lifecycle:
New from this manufacturer.
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