9FGP202A
FREQUENCY TIMING GENERATOR FOR PERIPHERALS
IDT®
FREQUENCY TIMING GENERATOR FOR PERIPHERALS 5
9FGP202A REV D 070511
Truth Table 1: VttPwr_GD/PD# and OE_96
VttPwr_GD/PD# OE_96
Pin 40 Pin 5
0 0 All clocks are powered down
0 1 All clocks are powered down
1 0 All clocks are enabled except DOT96SS
1 1 *All clocks are enabled including DOT96SS
*Assuming DOT96 Output Enable from SMBus Byte2 Bit0 sets to enable (default)
Clocks
Truth Table 2: VttPwr_GD/PD# and OE_CPU
VttPwr_GD/PD# OE_CPU
Pin 40 Pin 6
0 0 All clocks are powered down
0 1 All clocks are powered down
1 0 All clocks are enabled except CPUCLK
1 1 *All clocks are enabled including CPUCLK
*Assuming CPUCLK Output Enable from SMBus Byte2 Bit1 sets to enable (default)
Clocks
Table 1: CPU Spread and Frequency Selection
CPU
SS_EN
CPU
FS2
CPU
FS1
CPU
FS0
Byte 0
Bit 3
Byte 0
Bit 2
Byte 0
Bit 1
Byte 0
Bit 0
0
0 0 0 266.67 0%
0
0 0 1 133.33 0%
0
0 1 0 200.00 0%
0
0 1 1 166.67 0%
0
1 0 0 333.33 0%
0
1 0 1 100.00 0%
0
1 1 0 400.00 0%
0
1 1 1 200.00 0%
1
0 0 0 266.67
0.5%
1
0 0 1 133.33
0.5%
1
0 1 0 200.00
0.5%
1
0 1 1 166.67
0.5%
1
1 0 0 333.33
0.5%
1
1 0 1 100.00
0.5%
1
1 1 0 400.00
0.5%
1
1 1 1 200.00
0.5%
CPU
MHz
Down
Sp read %
