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MK22FN1M0VLQ12

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
e3984: SDHC: eSDHC misses SDIO interrupt when CINT is disabled
Errata type: Errata
Description: An issue is identified when interfacing the SDIO card. There is a case where an SDIO interrupt
from the card is not recognized by the hardware, resulting in a hang.
If the SDIO card lowers the DAT1 line (which indicates an interrupt) when the SDIO interrupt is
disabled in the eSDHC registers (that is, CINTEN bits in IRQSTATEN and IRQSIGEN are set
to zero), then, after the SDIO interrupt is enabled (by setting the CINTEN bits in IRQSTATEN
and IRQSIGEN registers), the eSDHC does not sense that the DAT1 line is low. Therefore, it
fails to set the CINT interrupt in IRQSTAT even if DAT1 is low.
Generally, CINTEN bit is disabled in interrupt service.
The SDIO interrupt service steps are as follows:
1. Clear CINTEN bit in IRQSTATEN and IRQSIGEN.
2. Reset the interrupt factors in the SDIO card and write 1 to clear the CINT interrupt in
IRQSTAT.
3. Re-enable CINTEN bit in IRQSTATEN and IRQSIGEN.
If a new SDIO interrupt from the card occurs between step 2 and step 3, the eSDHC skips it.
Workaround: The workaround interrupt service steps are as follows:
1. Clear CINTEN bit in IRQSTATEN and IRQSIGEN.
2. Reset the interrupt factors in the SDIO card and write 1 to clear CINT interrupt in IRQSTAT.
3. Clear and then set D3CD bit in the PROCTL register. Clearing D3CD bit sets the reverse
signal of DAT1 to low, even if DAT1 is low. After D3CD bit is re-enabled, the eSDHC can catch
the posedge of the reversed DAT1 signal, if the DAT1 line is still low.
4. Re-enable CINTEN bit in IRQSTATEN and IRQSIGEN.
e4218: SIM/FLEXBUS: SIM_SCGC7[FLEXBUS] bit should be cleared when the FlexBus
is not being used.
Errata type: Errata
Description: The SIM_SCGC7[FLEXBUS] bit is set by default. This means that the FlexBus will be enabled
and come up in global chip select mode.
With some code sequence and register value combinations the core could attempt to prefetch
from the FlexBus even though it might not actually use the value it prefetched. In the case
where the FlexBus is unconfigured, this can result in a hung bus cycle on the FlexBus.
Workaround: If the FlexBus is not being used, disabled the clock to the FlexBus during chip initialization by
clearing the SIM_SCGC7[FLEXBUS] bit.
If the FlexBus will be used, then enable at least one chip select as early in the chip initialization
process as possible.
e4935: UART: CEA709.1 features not supported
Errata type: Errata
Mask Set Errata for Mask 2N03G, Rev 26 AUG 2013
Freescale Semiconductor, Inc. 9
Description: Due to some issues that affect compliance with the specification, the CEA709.1 features of the
UART module are not supported. Normal UART mode, IrDA, and ISO-7816 are unaffected.
Workaround: Do not use the UART in CEA709.1 mode.
e7027: UART: During ISO-7816 T=0 initial character detection invalid initial characters
are stored in the RxFIFO
Errata type: Errata
Description: When performing initial character detection (UART_C7816[INIT] = 1) in ISO-7816 T=0 mode
with UART_C7816[ANACK] cleared, the UART samples incoming traffic looking for a valid
initial character. Instead of discarding any invalid initial characters that are received, the UART
will store them in the receive FIFO.
Workaround: After a valid initial charcter is detected (UART_IS7816[INITD] sets), flush the RxFIFO to
discard any invalid initial characters that might have been received before the valid initial
character.
e7028: UART: During ISO-7816 initial character detection the parity, framing, and noise
error flags can set
Errata type: Errata
Description: When performing initial character detection (UART_C7816[INIT] = 1) in ISO-7816 mode the
UART should not set error flags for any receive traffic before a valid initial character is
detected, but the UART will still set these error flags if any of the conditions are true.
Workaround: After a valid initial charcter is detected (UART_IS7816[INITD] sets), check the UART_S1[NF,
FE, and PF] flags. If any of them are set, then clear them.
e6472: UART: ETU compensation needed for ISO-7816 wait time (WT) and block wait
time (BWT)
Errata type: Errata
Description: When using the default ISO-7816 values for wait time integer (UARTx_WP7816T0[WI]), guard
time FD multiplier (UARTx_WF7816[GTFD]), and block wait time integer
(UARTx_WP7816T1[BWI]), the calculated values for Wait Time (WT) and Block Wait Time
(BWT) as defined in the Reference Manual will be 1 ETU less than the ISO-7816-3
requirement.
Workaround: To comply with ISO-7816 requirements, compensation for the extra 1 ETU is needed. This
compensation can be achieved by using a timer, such as the low-power timer (LPTMR), to
introduce a 1 ETU delay after the WT or BWT expires.
e4647: UART: Flow control timing issue can result in loss of characters if FIFO is not
enabled
Errata type: Errata
Mask Set Errata for Mask 2N03G, Rev 26 AUG 2013
10 Freescale Semiconductor, Inc.
Description: On UART0 and UART1 when /RTS flow control signal is used in receiver request-to-send
mode, the /RTS signal is negated if the number of characters in the Receive FIFO is equal to
or greater than the receive watermark. The /RTS signal will not negate until after the last
character (the one that makes the condition for /RTS negation true) is completely received and
recognized. This creates a delay between the end of the STOP bit and the negation of the /
RTS signal. In some cases this delay can be long enough that a transmitter will start
transmission of another character before it has a chance to recognize the negation of the /RTS
signal (the /CTS input to the transmitter).
Workaround: Always enable the RxFIFO if you are using flow control for UART0 or UART1. The receive
watermark should be set to seven or less. This will ensure that there is space for at least one
more character in the FIFO when /RTS negates. So in this case no data would be lost.
Note that only UART0 and UART1 are affected. The UARTs that do not have the RxFIFO
feature are not affected.
e7029: UART: In ISO-7816 T=1 mode, CWT interrupts assert at both character and
block boundaries
Errata type: Errata
Description: When operating in ISO-7816 T=1 mode and switching from transmission to reception block,
the character wait time interrupt flag (UART_IS7816[CWT]) should not be set, only block type
interrupts should be valid. However, the UART can set the CWT flag while switching from
transmit to receive block and at the start of transmit blocks.
Workaround: If a CWT interrupt is detected at a block boundary instead of a character boundary, then the
interrupt flag should be cleared and otherwise ignored.
e7090: UART: In ISO-7816 mode, timer interrupts flags do not clear
Errata type: Errata
Description: In ISO-7816, when any of the timer counter expires, the corresponding interrupt status register
bits gets set. The timer register bits cannot be cleared by software without additional steps,
because the counter expired signal remains asserted internally. Therefore, these bits can be
cleared only after forcing the counters to reload.
Workaround: Follow these steps to clear the UART_IS7816 WT, CWT, or BWT bits:
1. Clear the UART_C7816[ISO_7816E] bit, to temporarily disable ISO-7816 mode.
2. Write 1 to the WT, CWT, or BWT bits that need to be cleared.
3. Set UART_C7816[ISO_7816E] to re-enable ISO-7816 mode.
Note that the timers will start counting again as soon as the ISO_7816E bit is set. To avoid
unwanted timeouts, software might need to wait until new transmit or receive traffic is expected
or desired before re-enabling ISO-7816 mode.
e7031: UART: In single wire receive mode UART will attempt to transmit if data is
written to UART_D
Errata type: Errata
Mask Set Errata for Mask 2N03G, Rev 26 AUG 2013
Freescale Semiconductor, Inc. 11
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

MK22FN1M0VLQ12

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ARM Microcontrollers - MCU K20 1MB 120Mhz
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