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MK22FN1M0VLQ12

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3. Data length is less than or equal to 4 bytes (the length field of the corresponding descriptor
is set to 1, 2, 3, or 4) and the ADMA transfers one 32-bit word on the bus
4. Block Count Enable mode
Workaround: The software should avoid setting ADMA type last descriptor (TRANS descriptor with END
flag) to data length less than or equal to 4 bytes. In ADMA1 mode, if needed, a last NOP
descriptor can be appended to the descriptors list. In ADMA2 mode this workaround is not
feasible due to ERR003983.
e3982: SDHC: ADMA transfer error when the block size is not a multiple of four
Errata type: Errata
Description: Issue in eSDHC ADMA mode operation. The eSDHC read transfer is not completed when
block size is not a multiple of 4 in transfer mode ADMA1 or ADMA2. The eSDHC DMA
controller is stuck waiting for the IRQSTAT[TC] bit in the interrupt status register.
The following examples trigger this issue:
1. Working with an SD card while setting ADMA1 mode in the eSDHC
2. Performing partial block read
3. Writing one block of length 0x200
4. Reading two blocks of length 0x22 each. Reading from the address where the write
operation is performed. Start address is 0x512 aligned. Watermark is set as one word during
read. This read is performed using only one ADMA1 descriptor in which the total size of the
transfer is programmed as 0x44 (2 blocks of 0x22).
Workaround: When the ADMA1 or ADMA2 mode is used and the block size is not a multiple of 4, the block
size should be rounded to the next multiple of 4 bytes via software. In case of write, the
software should add the corresponding number of bytes at each block end, before the write is
initialized. In case of read, the software should remove the dummy bytes after the read is
completed.
For example, if the original block length is 22 bytes, and there are several blocks to transfer,
the software should set the block size to 24. The following data is written/stored in the external
memory:
4 Bytes valid data
4 Bytes valid data
4 Bytes valid data
4 Bytes valid data
4 Bytes valid data
2 Bytes valid data + 2 Byte dummy data
4 Bytes valid data
4 Bytes valid data
4 Bytes valid data
4 Bytes valid data
4 Bytes valid data
2 Bytes valid data + 2 Byte dummy data
Mask Set Errata for Mask 2N03G, Rev 26 AUG 2013
6 Freescale Semiconductor, Inc.
In this example, 48 (24 x 2) bytes are transferred instead of 44 bytes. The software should
remove the dummy data.
e4624: SDHC: AutoCMD12 and R1b polling problem
Errata type: Errata
Description: Occurs when a pending command which issues busy is completed. For a command with R1b
response, the proper software sequence is to poll the DLA for R1b commands to determine
busy state completion. The DLA polling is not working properly for the ESDHC module and
thus the DLA bit in PRSSTAT register cannot be polled to wait for busy state ompletion. This is
relevant for all eSDHC ports (eSDHC1-4 ports).
Workaround: Poll bit 24 in PRSSTAT register (DLSL[0] bit) to check that wait busy state is over.
e3977: SDHC: Does not support Infinite Block Transfer Mode
Errata type: Errata
Description: The eSDHC does not support infinite data transfers, if the Block Count register is set to one,
even when block count enable is not set.
Workaround: The following software workaround can be used instead of the infinite block mode:
1. Set BCEN bit to one and enable block count
2. Set the BLKCNT to the maximum value in Block Attributes Register (BLKATTR) (0xFFFFfor
65535 blocks)
e4627: SDHC: Erroneous CMD CRC error and CMD Index error may occur on sending
new CMD during data transfer
Errata type: Errata
Description: When sending new, non data CMD during data transfer between the eSDHC and EMMC card,
the module may return an erroneous CMD CRC error and CMD Index error. This occurs when
the CMD response has arrived at the moment the FIFO clock is stopped. The following bits
after the start bit of the response are wrongly interpreted as index, generating the CRC and
Index errors.
The data transfer itself is not impacted.
The rate of occurrence of the issue is very small, as there is a need for the following
combination of conditions to occur at the same cycle:
• The FIFO clock is stopped due to FIFO full or FIFO empty
• The CMD response start bit is received
Workaround: The recommendation is to not set FIFO watermark level to a too small value in order to reduce
frequency of clock pauses.
The problem is identified by receiving the CMD CRC error and CMD Index error. Once this
issue occurs, one can send the same CMD again until operation is successful.
Mask Set Errata for Mask 2N03G, Rev 26 AUG 2013
Freescale Semiconductor, Inc. 7
e3980: SDHC: Glitch is generated on card clock with software reset or clock divider
change
Errata type: Errata
Description: A glitch may occur on the SDHC card clock when the software sets the RSTA bit (software
reset) in the system control register. It can also be generated by setting the clock divider value.
The glitch produced can cause the external card to switch to an unknown state. The
occurrence is not deterministic.
Workaround: A simple workaround is to disable the SD card clock before the software reset, and enable it
when the module resumes the normal operation. The Host and the SD card are in a master-
slave relationship. The Host provides clock and control transfer across the interface.
Therefore, any existing operation is discarded when the Host controller is reset.
The recommended flow is as follows:
1. Software disable bit[3], SDCLKEN, of the System Control Register
2. Trigger software reset and/or set clock divider
3. Check bit[3], SDSTB, of the Present State Register for stable clock
4. Enable bit[3], SDCLKEN, of the System Control Register.
Using the above method, the eSDHC cannot send command or transfer data when there is a
glitch in the clock line, and the glitch does not cause any issue.
e3983: SDHC: Problem when ADMA2 last descriptor is LINK or NOP
Errata type: Errata
Description: ADMA2 mode in the eSDHC is used for transfers to/from the SD card. There are three types of
ADMA2 descriptors: TRANS, LINK or NOP. The eSDHC has a problem when the last
descriptor (which has the End bit '1') is a LINK descriptor or a NOP descriptor.
In this case, the eSDHC completes the transfers associated with this descriptor set, whereas it
does not even start the transfers associated with the new data command. For example, if a
WRITE transfer operation is performed on the card using ADMA2, and the last descriptor of
the WRITE descriptor set is a LINK descriptor, then the WRITE is successfully finished. Now, if
a READ transfer is programmed from the SD card using ADMA2, then this transfer does not go
through.
Workaround: Software workaround is to always program TRANS descriptor as the last descriptor.
e3978: SDHC: Software can not clear DMA interrupt status bit after read operation
Errata type: Errata
Description: After DMA read operation, if the SDHC System Clock is automatically gated off, the DINT
status can not be cleared by software.
Workaround: Set HCKEN bit before starting DMA read operation, to disable SDHC System Clock auto-
gating feature; after the DINT and TC bit received when read operation is done, clear HCKEN
bit to re-enable the SDHC System Clock auto-gating feature.
Mask Set Errata for Mask 2N03G, Rev 26 AUG 2013
8 Freescale Semiconductor, Inc.
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MK22FN1M0VLQ12

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ARM Microcontrollers - MCU K20 1MB 120Mhz
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