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MK22FN1M0VLQ12

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3) LDR SP,[Rn,#imm]
4) LDR SP,[Rn]
5) LDR SP,[Rn,Rm]
The affected instructions that can result in the stack-pointer being loaded from an incorrect
memory address are:
1) LDR SP,[Rn],#imm
2) LDR SP,[Rn,#imm]!
Conditions
1) An LDR is executed, with SP/R13 as the destination
2) The address for the LDR is successfully issued to the memory system
3) An interrupt is taken before the data has been returned and written to the stack-pointer.
Implications
Unless the load is being performed to Device or Strongly-Ordered memory, there should be no
implications from the repetition of the load. In the unlikely event that the load is being
performed to Device or Strongly-Ordered memory, the repeated read can result in the final
stack-pointer value being different than had only a single load been performed.
Interruption of the two write-back forms of the instruction can result in both the base register
value and final stack-pointer value being incorrect. This can result in apparent stack corruption
and subsequent unintended modification of memory.
Workaround: Both issues may be worked around by replacing the direct load to the stack-pointer, with an
intermediate load to a general-purpose register followed by a move to the stack-pointer.
If repeated reads are acceptable, then the base-update issue may be worked around by
performing the stack pointer load without the base increment followed by a subsequent ADD or
SUB instruction to perform the appropriate update to the base register.
e6940: Core: VDIV or VSQRT instructions might not complete correctly when very
short ISRs are used
Errata type: Errata
Description: ARM Errata 709718: VDIV or VSQRT instructions might not complete correctly when very
short ISRs are used
Affects: Cortex-M4F
Fault Type: Programmer Category B
Fault Status: Present in: r0p0, r0p1 Open.
On Cortex-M4 with FPU, the VDIV and VSQRT instructions take 14 cycles to execute. When
an interrupt is taken a VDIV or VSQRT instruction is not terminated, and completes its
execution while the interrupt stacking occurs. If lazy context save of floating point state is
enabled then the automatic stacking of the floating point context does not occur until a floating
point instruction is executed inside the interrupt service routine.
Lazy context save is enabled by default. When it is enabled, the minimum time for the first
instruction in the interrupt service routine to start executing is 12 cycles. In certain timing
conditions, and if there is only one or two instructions inside the interrupt service routine, then
the VDIV or VSQRT instruction might not write its result to the register bank or to the FPSCR.
Mask Set Errata for Mask 2N03G, Rev 26 AUG 2013
Freescale Semiconductor, Inc. 3
Workaround: A workaround is only required if the floating point unit is present and enabled. A workaround is
not required if the memory system inserts one or more wait states to every stack transaction.
There are two workarounds:
1) Disable lazy context save of floating point state by clearing LSPEN to 0 (bit 30 of the
FPCCR at address 0xE000EF34).
2) Ensure that every interrupt service routine contains more than 2 instructions in addition to
the exception return instruction.
e5706: FTFx: MCU security is inadvertently enabled (secured) if a mass erase is
executed when the flash blocks/halves are swapped. This issue only affects
applications that use the flash swap feature.
Errata type: Errata
Description: When the logical addresses of the flash blocks (halves) are swapped via the flash swap control
command sequence and a mass erase is executed (via the MDM-AP or EzPort), the MCU
security can go from un-secure to secure. Thus, when using a debugger to erase the entire
flash memory and re-download a software application, the debugger may report that the device
is secure after the erase completes. This issue only affects applications that use the flash
swap feature.
Workaround: Issue the mass erase request (via the MDM-AP or EzPort) a second time to un-secure the
device.
e4710: FTM: FTMx_PWMLOAD register does not support 8-/16-bit accesses
Errata type: Errata
Description: The FTM PWM Load register should support 8-bit and 16-bit accesses. However, the
FTMx_PWMLOAD[LDOK] bit is cleared automatically by FTM with these sized accesses, thus
disabling the loading of the FTMx_MOD, FTMx_CNTIN, and FTMx_CnV registers.
Workaround: Always use a 32-bit write access to modify contents of the FTMx_PWMLOAD register.
e6573: JTAG: JTAG TDO function on the PTA2 disables the pull resistor
Errata type: Errata
Description: The JTAG TDO function on the PTA2 pin disables the pull resistor, but keeps the input buffer
enabled. Because the JTAG will tri-state this pin during JTAG reset (or other conditions), this
pin will float with the input buffer enabled. If the pin is unconnected in the circuit, there can be
increased power consumption in low power modes for some devices.
Workaround: Disable JTAG TDO functionality when the JTAG interface is not needed and left floating in a
circuit. Modify the PORTA_PCR2 mux before entering low power modes. Set the mux to a pin
function other than ALT7. If set up as a digital input and left unconnected in the circuit, then a
pull-up or pull-down should be enabled. Alternatively, an external pull device or external source
can be added to the pin.
Note: Enabling the pull resistor on the JTAG TDO function violates the JTAG specification.
Mask Set Errata for Mask 2N03G, Rev 26 AUG 2013
4 Freescale Semiconductor, Inc.
e7214: Low Leakage Stop (LLS) mode non-functional
Errata type: Errata
Description: On some devices, system and peripheral memories may be corrupted when a device exits the
Low Leakage Stop (LLS) mode.
Workaround: All other low power modes are not affected. Use VLPS or VLLSx mode.
A silicon revision to correct the errata is planned.
e6665: Operating requirements: Limitation of the device operating range
Errata type: Errata
Description: Some devices, when power is applied, may not consistently begin to execute code under
certain voltage and temperature conditions. Applications that power up with either VDD >= 2.0
V or temperature >= -20C are not impacted. Entry and exit of low-power modes is not
impacted.
Workaround: To avoid this unwanted behavior, one or both of these conditions must be met:
a) Perform power on reset of the device with a supply voltage (VDD) equal-to or greater-than
2.0 V , or
b) Perform power on reset of the device at a temperature at or above -20 C.
e5130: SAI: Under certain conditions, the CPU cannot reenter STOP mode via an
asynchronous interrupt wakeup event
Errata type: Errata
Description: If the SAI generates an asynchronous interrupt to wake the core and it attempts to reenter
STOP mode, then under certain conditions the STOP mode entry is blocked and the
asynchronous interrupt will remain set.
This issue applies to interrupt wakeups due to the FIFO request flags or FIFO warning flags
and then only if the time between the STOP mode exit and subsequent STOP mode reentry is
less than 3 asynchronous bit clock cycles.
Workaround: Ensure that at least 3 bit clock cycles elapse following an asynchronous interrupt wakeup
event, before STOP mode is reentered.
e3981: SDHC: ADMA fails when data length in the last descriptor is less or equal to 4
bytes
Errata type: Errata
Description: A possible data corruption or incorrect bus transactions on the internal AHB bus, causing
possible system corruption or a stall, can occur under the combination of the following
conditions:
1. ADMA2 or ADMA1 type descriptor
2. TRANS descriptor with END flag
Mask Set Errata for Mask 2N03G, Rev 26 AUG 2013
Freescale Semiconductor, Inc. 5
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MK22FN1M0VLQ12

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ARM Microcontrollers - MCU K20 1MB 120Mhz
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