Description: While the UART_S1[FE] framing error flag is set the UART will discard any received data.
Even though the data is discarded, if characters are received that include noise or parity
errors, then the UART_S1[NF] or UART_S1[PE] bits can still set. This can lead to triggering of
unwanted interrupts if the parity or noise error interrupts are enabled and framing error
interrupts are disabled.
Workaround: If a framing error is detected (UART_S1[FE] = 1), then the noise and parity error flags can be
ignored until the FE flag is cleared. Note: the process to clear the FE bit will also clear the NF
and PE bits.
e7092: UART: UART_S1[TC] is not cleared by queuing a preamble or break character
Errata type: Errata
Description: The UART_S1[TC] flag can be cleared by first reading UART_S1 with TC set and then
performing one of the following: writing to UART_D, queuing a preamble, or queuing a break
character. If the TC flag is cleared by queuing a preamble or break character, then the flag will
clear as expected the first time. When TC sets again, the flag can be cleared by any of the
three clearing mechanisms without reading the UART_S1 register first. This can cause a TC
flag occurrence to be missed.
Workaround: If preamble and break characters are never used to clear the TC flag, then no workaround is
required.
If a preamble or break character is used to clear TC, then write UART_D immediately after
queuing the preamble or break character.
e5928: USBOTG: USBx_USBTRC0[USBRESET] bit does not operate as expected in all
cases
Errata type: Errata
Description: The USBx_USBTCR0[USBRESET] bit is not properly synchronized. In some cases using the
bit can cause the USB module to enter an undefined state.
Workaround: Do not use the USBx_USBTCR0[USBRESET] bit. If USB registers need to be written to their
reset states, then write those registers manually instead of using the module reset bit.
e6933: eDMA: Possible misbehavior of a preempted channel when using continuous
link mode
Errata type: Errata
Description: When using continuous link mode (DMA_CR[CLM] = 1) with a high priority channel linking to
itself, if the high priority channel preempts a lower priority channel on the cycle before its last
read/write sequence, the counters for the preempted channel (the lower priority channel) are
corrupted. When the preempted channel is restored, it runs past its "done" point instead of
performing a single read/write sequence and retiring.
The preempting channel (the higher priority channel) will execute as expected.
Mask Set Errata for Mask 2N03G, Rev 26 AUG 2013
Freescale Semiconductor, Inc. 13
