AD9841AJSTZRL Datasheet AD9841AJSTZRL, AD9841AJSTZ | P10-P12

REV. 0

AD9841A/AD9842A

–10–

CCD-MODE AND AUX MODE TIMING

N N+1 N+2 N+9 N+10

INH

N–10 N–9N–8N–1N

NOTES:

1. RECOMMENDED PLACEMENT FOR DATACLK RISING EDGE IS BETWEEN THE SHD RISING EDGE AND NEXT SHP FALLING EDGE.

2. CCD SIGNAL IS SAMPLED AT SHP AND SHD RISING EDGES.

SHP

SHD

DATACLK

OUTPUT

DATA

CCD

SIGNAL

Figure 5. CCD-Mode Timing

CCD

SIGNAL

EFFECTIVE PIXELS

CLPOB

CLPDM

OPTICAL BLACK PIXELS

HORIZONTAL

BLANKING

DUMMY PIXELS EFFECTIVE PIXELS

PBLK

NOTES:

1. CLPOB AND CLPDM WILL OVERWRITE PBLK. PBLK WILL NOT AFFECT CLAMP OPERATION IF OVERLAPPING CLPDM AND/OR CLPOB.

2. PBLK SIGNAL IS OPTIONAL.

3. DIGITAL OUTPUT DATA WILL BE ALL ZEROS DURING PBLK. OUTPUT DATA LATENCY IS 9 DATACLK CYCLES.

OUTPUT

DATA

EFFECTIVE PIXEL DATA OB PIXEL DATA DUMMY BLACK EFFECTIVE DATA

Figure 6. Typical CCD-Mode Line Clamp Timing

DATACLK

OUTPUT

DATA

VIDEO

SIGNAL

N+1

N+2

N+8

N+9

N–10 N–9N–8N–1N

Figure 7. AUX-Mode Timing

REV. 0

AD9841A/AD9842A

–11–

PIXEL GAIN AMPLIFIER (PxGA) TIMING

FRAME n

FRAME n+1

LINE 0 LINE 1 LINE 2 LINE m

0101... 2323... 0101...

LINE m–1 LINE 0 LINE 1 LINE 2 LINE m

0101... 2323...

0101...

LINE m–1

NOTE: 0 = GAIN0, 1 = GAIN1, 2 = GAIN2, 3 = GAIN3

Figure 8. PxGA Mode 1 (Mosaic Separate) Frame/Line Gain Register Sequence

SHP

PxGA

GAIN

3ns MIN

GAIN0

3ns MIN

GAIN1 GAIN0

NOTES:

1. MINIMUM PULSEWIDTH FOR HD AND VD IS 5 PIXEL CYCLES.

2. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES. MINIMUM SET-UP TIME IS 3ns.

3. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 0101.

4. EVERY HD RISING EDGE WITHOUT A PREVIOUS VD RISING EDGE WILL ALTERNATE BETWEEN 0101... AND 2323.

GAIN3

GAIN2

GAINXGAINX

5 PIXEL MIN

Figure 9. PxGA Mode 1 (Mosaic Separate) Detailed Timing

EVEN FIELD ODD FIELD

0101... 2323... 0101...

NOTE: 0 = GAIN0, 1 = GAIN1, 2 = GAIN2, 3 = GAIN3

0101... 2323...

0101...

LINE 0 LINE 1 LINE 2 LINE mLINE m–1 LINE 0 LINE 1 LINE 2 LINE mLINE m–1

Figure 10. PxGA Mode 2 (Interlace) Frame/Line Gain Register Sequence

SHP

PxGA

GAIN

3ns MIN

GAIN0

3ns MIN

GAIN1 GAIN0

GAIN3GAIN2

GAINX

5 PIXEL MIN

NOTES:

1. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES.

2. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING OR FALLING EDGE WILL RESET TO 0101.

3. EVERY HD RISING EDGE WITHOUT A PREVIOUS VD RISING EDGE WILL ALTERNATE BETWEEN 0101... AND 2323.

Figure 11. PxGA Mode 2 (Interlace) Detailed Timing

REV. 0

AD9841A/AD9842A

–12–

NOTE: 0 = GAIN0, 1 = GAIN1, 2 = GAIN2

LINE n LINE n+1

012012012... 012012012......01201

Figure 12. PxGA Mode 3 (3-Color) Frame/Line Gain Register Sequence

SHP

PxGA

GAIN

GAIN1

GAIN2 GAIN0

GAIN1GAIN0

GAINXGAIN0GAINX

3ns MIN

5 PIXEL MIN

NOTES:

1. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES.

2. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 012012.

Figure 13. PxGA Mode 3 (3-Color) Detailed Timing

NOTE: 0 = GAIN0, 1 = GAIN1, 2 = GAIN2, 3 = GAIN3

LINE n LINE n+1

012301230123......0123001230123012...

Figure 14. PxGA Mode 4 (4-Color) Frame/Line Gain Register Sequence

SHP

PxGA

GAIN

GAIN1

GAIN2 GAIN0

GAIN1GAIN0

GAINXGAIN0GAINX

3ns MIN

5 PIXEL MIN

NOTES:

1. BOTH VD AND HD ARE INTERNALLY UPDATED AT SHP RISING EDGES.

2. EVERY HD RISING EDGE WITH A PREVIOUS VD RISING EDGE WILL RESET TO 01230123.

Figure 15. PxGA Mode 4 (4-Color) Detailed Timing

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P23

AD9841AJSTZRL

Mfr. #:

Buy AD9841AJSTZRL

Manufacturer:

Analog Devices Inc.

Description:

Analog Front End - AFE 10-Bit 20MHz CCD Signal Processor

Lifecycle:

New from this manufacturer.

Delivery:

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AD9841AJSTZRL

AD9841AJSTZRL

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