REV. 0
AD9841A/AD9842A
–19–
RR
Gb Gb
Gr
Gr
BB
CCD: PROGRESSIVE BAYER
LINE0 GAIN0, GAIN1, GAIN0, GAIN1 ...
RR
Gr
Gr
Gb GbBB
LINE1
LINE2
GAIN2, GAIN3, GAIN2, GAIN3 ...
GAIN0, GAIN1, GAIN0, GAIN1 ...
MOSAIC SEPARATE COLOR
STEERING MODE
Figure 26. CCD Color Filter Example: Progressive Scan
LINE0 GAIN0, GAIN1, GAIN0, GAIN1 ...
RR
Gr
Gr
LINE1
LINE2
GAIN0, GAIN1, GAIN0, GAIN1 ...
GAIN0, GAIN1, GAIN0, GAIN1 ...
Gb GbBB
LINE0 GAIN2, GAIN3, GAIN2, GAIN3 ...
LINE1
LINE2
GAIN2, GAIN3, GAIN2, GAIN3 ...
GAIN2, GAIN3, GAIN2, GAIN3 ...
CCD: INTERLACED BAYER
EVEN FIELD
VD SELECTED COLOR
STEERING MODE
ODD FIELD
Gb GbBB
Gb GbBB
Gb GbBB
RR
Gr
Gr
RR
Gr
Gr
RR
Gr
Gr
Figure 27. CCD Color Filter Example: Interlaced
The same Bayer pattern can also be interlaced, and the VD
Selected mode should be used with this type of CCD (see Fig-
ure 27). The Color Steering performs the proper multiplexing of
the R, G, and B gain values (loaded into the PxGA
gain regis-
ters), and is synchronized by the user with vertical (VD) and
horizontal (HD) sync pulses. For more detailed information, see
the PxGA
Timing section. The PxGA
gain for each of the four
channels is variable from –2 dB to +10 dB, controlled in 64 steps
through the serial interface. The PxGA
gain curve is shown in
Figure 28.
PxGA GAIN REGISTER CODE
10
32
PxGA GAIN dB
40 48 56 0 8 16 24 31
8
6
4
2
0
-2
(100000)
(011111)
Figure 28. PxGA Gain Curve
Variable Gain Amplifier
The VGA stage provides a gain range of 2 dB to 36 dB, program-
mable with 10-bit resolution through the serial digital interface.
Combined with 4 dB from the PxGA
stage, the total gain range
for the AD984xA is 6 dB to 40 dB. The minimum gain of 6 dB
is needed to match a 1 V input signal with the ADC full-scale
range of 2 V. When compared to 1 V full-scale systems (such as
ADI’s AD9803), the equivalent gain range is 0 dB to 34 dB.
The VGA gain curve is divided into two separate regions. When
the VGA Gain Register code is between 0 and 511, the curve
follows a (1 + x)/(1 – x) shape, which is similar to a “linear-in-
dB” characteristic. From code 512 to code 1023, the curve follows
a “linear-in-dB” shape. The exact VGA gain can be calculated
for any Gain Register value by using the following two equations:
Code Range Gain Equation (dB)
0–511 Gain = 20 log
10
([658 + code]/[658 – code]) – 0.4
512 –1023 Gain = (0.0354)(code) – 0.4
As shown in the CCD Mode Specifications, only the VGA gain
range from 2 dB to 36 dB has tested and guaranteed accuracy.
This corresponds to a VGA gain code range of 91 to 1023. The
Gain Accuracy Specifications also include the PxGA
gain of 4 dB,
for a total gain range of 6 dB to 40 dB.
VGA GAIN REGISTER CODE
36
0
VGA GAIN dB
127 255 383 511 639 767 895 1023
30
24
18
12
6
0
Figure 29. VGA Gain Curve (Gain from PxGA Not Included)
Optical Black Clamp
The optical black clamp loop is used to remove residual offsets
in the signal chain, and to track low-frequency variations in the
CCD’s black level. During the optical black (shielded) pixel
interval on each line, the ADC output is compared with a fixed
black level reference, selected by the user in the Clamp Level
Register. Any value between 0 LSB and 64 LSB (AD9841A)
or 255 LSB (AD9842A) may be programmed, with 8-bit resolu-
tion. The resulting error signal is filtered to reduce noise, and
the correction value is applied to the ADC input through a
D/A converter. Normally, the optical black clamp loop is turned
on once per horizontal line, but this loop can be updated more
slowly to suit a particular application. If external digital clamping
is used during the post processing, the AD984xA’s optical black
clamping may be disabled using Bit D5 in the Operation Register
(see Serial Interface Timing and Internal Register Description
section). When the loop is disabled, the Clamp Level Register
may still be used to provide programmable offset adjustment.
Horizontal timing is shown in Figure 6. The CLPOB pulse
should be placed during the CCD’s optical black pixels. It is
recommended that the CLPOB pulse duration be at least 20
pixels wide to minimize clamp noise. Shorter pulsewidths may be
used, but clamp noise may increase, and the ability to track
low-frequency variations in the black level will be reduced.
REV. 0
AD9841A/AD9842A
–20–
A/D Converter
The AD9841A and AD9842A use high-performance ADC archi-
tectures, optimized for high speed and low power. Differential
Nonlinearity (DNL) performance is typically better than 0.5 LSB,
as shown in TPCs 2 and 4. Instead of the 1 V full-scale range
used by the earlier AD9801 and AD9803 products from Analog
Devices, the AD984xA ADCs use a 2 V input range. Better
noise performance results from using a larger ADC full-scale
range (see TPCs 3 and 5).
AUX1 Mode
For applications that do not require CDS, the AD9841A/AD9842A
can be configured to sample ac-coupled waveforms. Figure 30
shows the circuit configuration for using the AUX1 channel
input (Pin 36). A single 0.1 µF ac-coupling capacitor is needed
between the input signal driver and the AUX1IN pin. An on-chip
dc-bias circuit sets the average value of the input signal to
approximately 0.4 V, which is referenced to the midscale code
of the ADC. The VGA Gain register provides a gain range of 0 dB
to 36 dB in this mode of operation (see VGA Gain Curve,
Figure 29). The VGA gains up the signal level with respect to
the 0.4 V bias level. Signal levels above the bias level will be
further increased to a higher ADC code, while signal levels below
the bias level will be further decreased to a lower ADC code.
AUX2 Mode
For sampling video-type waveforms, such as NTSC and PAL
signals, the AUX2 channel provides black level clamping, gain
adjustment, and A/D conversion. Figure 31 shows the circuit
configuration for using the AUX2 channel input (Pin 34). A
external 0.1 µF blocking capacitor is used with the on-chip video
clamp circuit, to level-shift the input signal to a desired refer-
ence level. The clamp circuit automatically senses the most
negative portion of the input signal, and adjusts the voltage
across the input capacitor. This forces the black level of the
input signal to be equal to the value programmed into the Clamp
Level register (see Serial Interface Register Description). The VGA
provides gain adjustment from 0 dB to 18 dB. The same VGA
Gain register is used, but only the 9 MSBs of the gain register
are used (see Table VIII.)
AUX1IN
0.1F
VGA GAIN
REGISTER
ADCVGA
10
5k
0.4V
0.4V
INPUT SIGNAL
??V
0.8V
0.4V
MIDSCALE
0dB TO 36dB
Figure 30. AUX1 Circuit Configuration
0dB TO 18dB
8
AUX2IN
BUFFER
0.1F
VIDEO
SIGNAL
9
CLAMP LEVEL
LPF
VGA GAIN
REGISTER
ADC
VGA
VIDEO CLAMP
CIRCUIT
CLAMP LEVEL
REGISTER
Figure 31. AUX2 Circuit Configuration
Table VIII. VGA Gain Register Used for AUX2-Mode
MSB LSB
D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Gain (dB)
X0 XXXXXXXXX0.0
10000000000.0
••
••
••
111111111118.0
REV. 0
AD9841A/AD9842A
–21–
CCD
CCDIN
BUFFER
V
OUT
0.1F
AD984xA
ADC
OUT
REGISTER
DATA
SERIAL
INTERFACE
DIGITAL
OUTPUTS
DIGITAL IMAGE
PROCESSING
ASIC
TIMING
GENERATOR
V-DRIVE
CCD
TIMING
CDS/CLAMP
TIMING
Figure 32. AD984xA System Applications Diagram
36
35
34
33
32
31
30
29
28
27
26
25
13 14 15 16 17 18 19 20 21 22 23 24
1
2
3
4
5
6
7
8
9
10
11
12
3748 47 46 45 44 39 3843 42 41 40
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
AUX1IN
AVSS
AUX2IN
AVDD2
BYP4
NC
CCDIN
BYP2
BYP1
AVDD1
AVSS
AVSS
NC
NC
(LSB) D0
D1
D2
D3
D4
D5
D6
D7
D8
(MSB) D9
AD9841A
SCK
SDATA
SL
NC
STBY
NC
THREE-STATE
DVSS
DVDD2
VRB
VRT
CML
DRVDD
DRVSS
DVSS
DATACLK
DVDD1
HD
PBLK
CLPOB
SHP
SHD
CLPDM
VD
0.1F
0.1F
0.1F
0.1F
0.1F
0.1F
3V
ANALOG SUPPLY
CCD SIGNAL
3V
ANALOG SUPPLY
10
DATA
OUTPUTS
3
SERIAL
INTERFACE
0.1F
1.0F
1.0F
0.1F
3V
ANALOG SUPPLY
8
CLOCK
INPUTS
0.1F
0.1F
3V
ANALOG SUPPLY
3V
DRIVER
SUPPLY
NC = NO CONNECT
Figure 33. AD9841A Recommended Circuit Configuration for CCD-Mode
APPLICATIONS INFORMATION
The AD9841A and AD9842A are complete Analog Front End
(AFE) products for digital still camera and camcorder appli-
cations. As shown in Figure 32, the CCD image (pixel) data is
buffered and sent to the AD984xA analog input through a series
input capacitor. The AD984xA performs the dc restoration,
CDS, gain adjustment, black level correction, and analog-to-
digital conversion. The AD984xA’s digital output data is then
processed by the image processing ASIC. The internal regis-
ters of the AD984xA—used to control gain, offset level, and other
functions—are programmed by the ASIC or microprocessor
through a 3-wire serial digital interface. A system timing gen-
erator provides the clock signals for both the CCD and the AFE.

AD9841AJSTZRL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog Front End - AFE 10-Bit 20MHz CCD Signal Processor
Lifecycle:
New from this manufacturer.
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