REV. 0
AD9841A/AD9842A
–15–
SDATA
SCK
SL
RNW TEST BIT
0
A2 0A0 A1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
t
DS
t
DH
t
LS
t
LH
NOTES:
1. SDATA BITS ARE INTERNALLY LATCHED ON THE RISING EDGES OF SCK.
2. RNW = READ-NOT WRITE. SET LOW FOR WRITE OPERATION.
3. TEST BITS = INTERNAL USE ONLY. MUST BE SET LOW.
4. SYSTEM UPDATE OF LOADED REGISTERS OCCURS ON SL RISING EDGE.
Figure 21. Serial Write Operation
SDATA
SCK
SL
RNW TEST BIT
10
0
A0 A1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
t
DS
t
DH
t
LS
t
LH
NOTES:
1. RNW = READ-NOT WRITE. SET HIGH FOR READ OPERATION.
2. TEST BITS = INTERNAL USE ONLY. MUST BE SET LOW.
3. SERIAL DATA FROM THE SELECTED REGISTER IS VALID STARTING AFTER THE 5TH SCK FALLING EDGE, AND IS UPDATED ON
SCK FALLING EDGES.
t
DV
Figure 22. Serial Readback Operation
SERIAL INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION
Table I. AD9841A/AD9842A Internal Register Map
Register Address Data Bits
Name A0 A1 A2 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10
Operation 0 0 0 Channel Select Power-Down Software OB Clamp 0* 1** 0* 0* 0*
CCD/AUX1/2 Modes Reset On/Off
VGA Gain 1 0 0 LSB MSB X
Clamp Level 0 1 0 LSB MSB X X X
Control 1 1 0 Color Steering Mode PxGA Clock Polarity Select for 0* 0* Three- X
Selection On/Off SHP/SHD/CLP/DATA State
PxGA Gain0 0 0 1 LSB MSB X X X X X
PxGA Gain1 1 0 1 LSB MSB X X X X X
PxGA Gain2 0 1 1 LSB MSB X X X X X
PxGA Gain3 1 1 1 LSB MSB X X X X X
*
Internal use only. Must be set to zero.
**
Must be set to one.
