The MAX1168 features a 16-bit-wide data-transfer
mode that includes a longer acquisition time (11.5
clock cycles). Longer acquisition times are useful in
applications with input source resistances greater than
1kΩ. Noise increases when using large source resis-
tances. To improve the input signal bandwidth under
AC conditions, drive AIN_ with a wideband buffer
(>10MHz) that can drive the ADC’s input capacitance
and settle quickly.
Input Bandwidth
The ADC’s input-tracking circuitry has a 4MHz small-
signal bandwidth, making possible the digitization of
high-speed transient events and the measurement of
periodic signals with bandwidths exceeding the ADC’s
sampling rate by using undersampling techniques. To
avoid aliasing of unwanted, high-frequency signals into
the frequency band of interest, use anti-alias filtering.
Analog Input Protection
Internal protection diodes, which clamp the analog
input to AV
DD
or AGND, allow the input to swing from
(AGND - 0.3V) to (AV
DD
+ 0.3V) without damaging the
device. If the analog input exceeds 300mV beyond the
supplies, limit the input current to 10mA.
MAX1167/MAX1168
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
______________________________________________________________________________________ 13
REFERENCE
REF
REFCAP
AV
DD
DV
DD
AGND
AGND DGND
AIN0
AIN1
AIN2
AIN3
SCLK
CS
DIN
ANALOG-INPUT
MULTIPLEXER
MULTIPLEXER
CONTROL
ACCUMULATOR
MEMORY
INPUT REGISTER
BIAS
OSCILLATOR
OUTPUT DOUT
EOC
ANALOG-SWITCH FINE TIMING
SUCCESSIVE-APPROXIMATION
REGISTER
MAX1168
DAC
BUFFER
AIN4
AIN5
AIN6
AIN7
AZ
RAIL
COMPARATOR
DSPX
DSEL
DSPR
Figure 4. MAX1168 Functional Diagram
MAX1167/MAX1168
Digital Interface
The MAX1167/MAX1168 feature an SPI/QSPI/
MICROWIRE-compatible, 3-wire serial interface. The
MAX1167 digital interface consists of digital inputs CS,
SCLK, and DIN and outputs DOUT and EOC. The
MAX1167 operates in the following modes:
SPI interface with external clock
SPI interface with internal clock
SPI interface with internal clock and scan mode
In addition to the standard 3-wire serial interface modes,
the MAX1168 includes a DSPR input and a DSPX output
for communicating with DSPs in external clock mode and
a DSEL input to determine 8-bit-wide or 16-bit-wide data-
transfer mode. When not using the MAX1168 in the DSP
interface mode, connect DSPR to DV
DD
and leave DSPX
unconnected.
Command/Configuration/Control Register
Table 1 shows the contents of the command/configura-
tion/control register and the state of each bit after initial
power-up. Tables 2–6 define the control and configuration
of the device for each bit. Cycling the power supplies
resets the command/configuration/control register to the
power-on-reset default state.
Initialization After Power-Up
A logic high on CS places the MAX1167/MAX1168 in
the shutdown mode chosen by the power-down bits,
and places DOUT in a high-impedance state. Drive CS
low to power up and enable the MAX1167/MAX1168
before starting a conversion. In internal reference
mode, allow 5ms for the shutdown internal reference
and/or buffer to wake and stabilize before starting a
conversion. In external reference mode (or if the inter-
nal reference is already on), no reference settling time
is needed after power-up.
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
14 ______________________________________________________________________________________
SCLK
DOUT
AGND
DGND
AIN0
REF
AV
DD
DV
DD
DOUT
SCLK
CS
+5V
DIN
ANALOG
INPUTS
+5V
1μF
0.1μF
0.1μF
GND
MAX1167
0.1μF
AIN1
AIN2
AIN3
DIN
EOC
EOC
AGND
REFCAP
CS
Figure 5. MAX1167 Typical Operating Circuit
SCLK
DOUT
AGND
DGND
AIN0
REF
AV
DD
DV
DD
DOUT
SCLK
CS
+5V
16
8
DIN
ANALOG
INPUTS
+5V
1μF
0.1μF
0.1μF
GND
MAX1168
0.1μF
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
DIN
DSEL
DSPR
DSPX
DSPX
EOC
AGND
REFCAP
EOC
CS
Figure 6. MAX1168 T ypical Operating Circuit
AUTOZERO
RAIL
CAPACITIVE
DAC
C
DAC
REF
AGND
TRACK
HOLD
HOLD TRACK
ZERO
MUX
R
IN
R
DSON
AIN_
C
MUX
C
SWITCH
Figure 7. Equivalent Input Circuit
BIT7 (MSB) BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0 (LSB)
COMMAND
CH SEL2 CH SEL1 CH SEL0 SCAN1 SCAN0 REF/PD_SEL1 REF/PD SEL0 INT/EXT CLK
POWER-UP
STATE
00000110
Table 1. Command/Configuration/Control Register
MAX1167/MAX1168
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
______________________________________________________________________________________ 15
BIT7 BIT6 BIT5
CH SEL2 CH SEL1 CH SEL0
CHANNEL
AIN_
000 0
001 1
010 2
011 3
100 4
101 5
110 6
111 7
Table 2. Channel Select
BIT4 BIT3
ACTION
SCAN1 SCAN0
Single channel, no scan 0 0
Sequentially scan channels 0 through N
(N 3)
01
Sequentially scan channels 2 through N
(2 N 3)
10
Scan channel N four times 1 1
Table 3. MAX1167 Scan Mode, Internal
Clock Only
BIT4 BIT3
ACTION
SCAN1 SCAN0
Single channel, no scan 0 0
Sequentially scan channels 0 through N
(N 7)
01
Sequentially scan channels 4 through N
(4 N 7)
10
Scan channel N eight times 1 1
Table 4. MAX1168 Scan Mode, Internal
Clock Only (Not for DSP Mode)
BIT2 BIT1
REF/PD_
SEL1
REF/PD
SEL0
REFERENCE
REFERENCE MODE
(INTERNAL REFERENCE)
TYPICAL
SUPPLY
CURRENT
TYPICAL WAKE-
UP TIME
(C
REF
= 1µF)
0 0 Internal
Internal reference and reference buffer on
between conversions
1mA NA
0 1 Internal
Internal reference and reference buffer off
between conversions
0.6µA 5ms
1 0 Internal
Internal reference on, reference buffer off
between conversions
0.43mA 5ms
1 1 External Internal reference and buffer always off 0.6µA NA
Table 5. Power-Down Modes
BIT0
INT/EXT
CLK
CLOCK MODE
0 External clock
1 Internal clock
Table 6. Clock Modes

MAX1168CCEG+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC Integrated Circuits (ICs) Analog to Digital Converters - IC ADC 16BIT 200KSPS 24-QSOP
Lifecycle:
New from this manufacturer.
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