MAX1167/MAX1168
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
______________________________________________________________________________________ 25
Digital Noise
Digital noise can couple to AIN_ and REF. The conversion
clock (SCLK) and other digital signals active during input
acquisition contribute noise to the conversion result.
Noise signals, synchronous with the sampling interval,
result in an effective input offset. Asynchronous signals
produce random noise on the input, whose high-frequen-
cy components can be aliased into the frequency band
of interest. Minimize noise by presenting a low imped-
ance (at the frequencies contained in the noise signal) at
the inputs. This requires bypassing AIN_ to AGND, or
buffering the input with an amplifier that has a small-sig-
nal bandwidth of several megahertz (doing both is prefer-
able). AIN has a typical bandwidth of 4MHz.
Distortion
Avoid degrading dynamic performance by choosing an
amplifier with distortion much less than the total har-
monic distortion of the MAX1167/MAX1168 at the fre-
quencies of interest (THD = -100dB at 1kHz). If the
chosen amplifier has insufficient common-mode rejec-
tion, which results in degraded THD performance, use
the inverting configuration (positive input grounded) to
eliminate errors from this source. Low-temperature-
coefficient, gain-setting resistors reduce linearity errors
caused by resistance changes due to self-heating. To
reduce linearity errors due to finite amplifier gain, use
amplifier circuits with sufficient loop gain at the fre-
quencies of interest.
DC Accuracy
To improve DC accuracy, choose a buffer with an offset
much less than the MAX1167/MAX1168s’ offset (±10mV
max for +5V supply), or whose offset can be trimmed
while maintaining stability over the required temperature
range.
DOUT*
CS
SCLK
*WHEN CS IS HIGH, DOUT = HIGH-Z
MSB
2016
D15 D14 D13 D12 D11 D10 D9
HIGH-Z
D1 D0
24
1214 86
D8 D5 D4 D3
LSB
D7 D6
SAMPLING INSTANT
D2
Figure 21b. QSPI Interface Timing Sequence (External Clock, 8-Bit Data Transfer, CPOL = CPHA = 0)
CONTROL BIT SETTINGS SYNCHRONOUS SERIAL-PORT STATUS REGISTER (SSPSTAT)
SMP BIT7 0
SPI Data-Input Sample Phase. Input data is sampled at the middle of
the data output time.
CKE BIT6 1
SPI Clock Edge-Select Bit. Data is transmitted on the rising edge of the
serial clock.
D/A BIT5 X Data Address Bit
P BIT4 X Stop Bit
S BIT3 X Start Bit
R/W BIT2 X Read/Write Bit Information
UA BIT1 X Update Address
BF BIT0 X Buffer-Full Status Bit
Table 8. Detailed SSPSTAT Register Contents
X = Don’t care.
SCK
SDI
GND
PIC16/17
I/O
SCLK
DOUT
CS
V
DD
V
DD
MAX1167
MAX1168
Figure 22a. SPI-Interface Connection for a PIC16/PIC17
MAX1167/MAX1168
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
26 ______________________________________________________________________________________
DOUT*
CS
SCLK
1ST BYTE READ
2ND BYTE READ
*WHEN CS IS HIGH, DOUT = HIGH-Z
MSB
HIGH-Z
3RD BYTE READ
LSB
D1 D0D7 D6 D5 D4 D3 D2
24
20
16128641
D15
D14 D13 D12 D11 D10 D9 D8
00000000
Figure 22b. SPI Interface Timing with PIC16/PIC17 in Master Mode (CKE = 1, CKP = 0, SMP = 0, SSPM3 - SSPM0 = 0001)
Serial Interfaces
SPI and MICROWIRE Interfaces
When using the SPI (Figure 20a) or MICROWIRE (Figure
20b) interfaces, set CPOL = 0 and CPHA = 0. Drive CS
low to power on the MAX1167/MAX1168 before starting a
conversion (Figure 20c). Three consecutive 8-bit-wide
readings are necessary to obtain the entire 16-bit result
from the ADC. DOUT data transitions on the serial clock’s
falling edge. The first 8-bit-wide data stream contains all
leading zeros. The 2nd 8-bit-wide data stream contains
the MSB through D6. The 3rd 8-bit-wide data stream con-
tains D5 through D0 followed by S1 and S0.
QSPI Interface
Using the high-speed QSPI interface with CPOL = 0 and
CPHA = 0, the MAX1167/MAX1168 support a maximum
f
SCLK
of 4.8MHz. Figure 21a shows the MAX1167/
MAX1168 connected to a QSPI master, and Figure 21b
shows the associated interface timing.
PIC16 with SSP Module and PIC17
Interface
The MAX1167/MAX1168 are compatible with a
PIC16/PIC17 controller (µC), using the synchronous seri-
al-port (SSP) module.
To establish SPI communication, connect the controller
as shown in Figure 22a and configure the PIC16/PIC17
as system master by initializing its synchronous serial-
port control register (SSPCON) and synchronous serial-
port status register (SSPSTAT) to the bit patterns shown
in Tables 7 and 8.
In SPI mode, the PIC16/PIC17 µCs allow 8 bits of data to
be synchronously transmitted and received simultane-
ously. Three consecutive 8-bit-wide readings (Figure
22b) are necessary to obtain the entire 16-bit result from
the ADC. DOUT data transitions on the serial clock’s
falling edge and is clocked into the µC on SCLK’s rising
edge. The first 8-bit-wide data stream contains all zeros.
The 2nd 8-bit-wide data stream contains the MSB
through D6. The 3rd 8-bit-wide data stream contains bits
D5 through D0 followed by S1 and S0.
DSP
EXTERNAL
CLOCK
SCLK
DSPR
DSPX
DIN
DOUT
SCLK
TFS
RFS
DT
DR
FL1
CS
MAX1168
Figure 23. DSP Interface Connection
MAX1167/MAX1168
Multichannel, 16-Bit, 200ksps Analog-to-Digital
Converters
______________________________________________________________________________________ 27
DSP Interface
The DSP mode of the MAX1168 only operates in exter-
nal clock mode. Figure 23 shows a typical DSP interface
connection to the MAX1168. Use the same oscillator as
the DSP to provide the clock signal for the MAX1168.
The DSP provides the falling edge at CS to wake the
MAX1168. The MAX1168 detects the state of DSPR on
the falling edge of CS (Figure 17). Logic low at DSPR
places the MAX1168 in DSP mode. After the MAX1168
enters DSP mode, CS can be left low. A frame sync
pulse from the DSP to DSPR initiates a conversion. The
MAX1168 sends a frame sync pulse from DSPX to the
DSP signaling that the MSB is available at DOUT. Send
another frame sync pulse from the DSP to DSPR to
begin the next conversion. The MAX1168 does not oper-
ate in scan mode when using DSP mode.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. The
static linearity parameters for the MAX1167/MAX1168
are measured using the end-point method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step-width and the ideal value of ±1 LSB. A
DNL error specification of ±1 LSB guarantees no miss-
ing codes and a monotonic transfer function.
Aperture Definitions
Aperture jitter (t
AJ
) is the sample-to-sample variation in
the time between samples. Aperture delay (t
AD
) is the
time between the falling edge of the sampling clock
and the instant when the actual sample is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital
samples, signal-to-noise ratio (SNR) is the ratio of the
full-scale analog input (RMS value) to the RMS quanti-
zation error (residual error). The ideal, theoretical mini-
mum analog-to-digital noise is caused by quantization
noise error only and results directly from the ADC’s res-
olution (N bits):
SNR = (6.02
N + 1.76)dB
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five har-
monics, and the DC offset.
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all the other ADC output signals:
SINAD (dB) = 20 log [Signal
RMS
/ (Noise +
Distortion)
RMS
]
EFFECTIVE NUMBER OF BITS (ENOB)
FREQUENCY (kHz)
EFFECTIVE BITS
101
2
4
6
8
10
12
14
16
0
0.1 100
f
SAMPLE
= 200ksps
Figure 24. Effective Bits vs. Frequency
SCLK
DOUT
AGND
DGND
AIN_
REF
AV
DD
DV
DD
DOUT
SCLK
CS
AIN_
+5V
10Ω
1μF
0.1μF
0.1μF
GND
MAX1167
MAX1168
AGND
CS
Figure 25. Powering AV
DD
and DV
DD
from a Single Supply

MAX1168CCEG+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC Integrated Circuits (ICs) Analog to Digital Converters - IC ADC 16BIT 200KSPS 24-QSOP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union