NCV70514
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18
Whenever <IRUN[3:0]> or <IHOLD[3:0]> is changed, the
new coil currents will be updated immediately at the next
PWM period.
In case the motor is disabled (<MOTEN>=0), the logic is
functional and both RHB pin and <RHBP> bit will have
effect on NXT/DIR operation (not on the H−bridges). When
the chip is in sleep mode, the logic is not functional and as
a result, the RHB pin will have no effect.
The logic state of the RHB pin is visible as a flag in SPI
status register.
Note:
The hard−reset function is embedded in the “Hold
mode” by means of a special sequence on the DIR pin, see
also Hard−Reset Function chapter.
Under−voltage Detection
The NCV70514 has three UV threshold levels. Two
higher threshold levels are programmable over SPI register
UVxThr, third threshold level is fixed.
Each UV level has its own flag readable via SPI and can
create interrupt to microcontroller when dedicated bit of
interrupt enable register is set.
All interrupt sources UV’s, BEMF, etc. are grouped
into single interrupt line (pin) ERRB.
When supply voltage VBB drops under dedicated UVx
level, several actions are performed.
• UV1 level – no action inside device regarding to
H−bridges – only when UV1IntEn interrupt enable bit
is set, ERRB pin is pulled down. Microcontroller needs
to do action like Soft stop, etc based on this interrupt.
• UV2 level – when UV2IntEn interrupt enable bit is set,
ERRB pin is pulled down. When UV2MIntEn interrupt
enable bit is set, the ERRB pin is pulled down in the
moment NXP pulse comes, the device then stops
executing NXT pulses and starts counting them in Step
loss counter <Sl[6:0]>.
• UV3 level – device each time disables H−Bridge
drivers (<MOTEN> = 0). When UV3IntEn interrupt
enable bit is set, ERRB pin is pulled down. When
UV3MIntEn interrupt enable bit is set, the ERRB pin is
pulled down in the moment NXP pulse comes, the
device then stops executing NXT pulses and starts
counting them in Step loss counter <Sl[6:0]>.
Only if the <UV3>=0 the motor can be enabled again
by writing <MOTEN>=1 in the control register 1.
Note:
The change of DIR and step mode will not be taken
into account in Step loss counter.
Step loss register range is 7 bits => 0 to 127 NXT pulses, no
overflow, keeping the counter at maximum value of 127 if
more than 127 NXT pulses are received.
Table 12. UV1/2 THRESHOLDS SETTINGS (4BIT)
UVxThr Index UV1/2 Threshold Level (V)
0 5.98
1 6.31
2 6.65
3 6.98
4 7.31
5 7.64
6 7.97
7 8.31
8 8.64
9 8.97
A 9.3
B 9.63
C 9.97
D 10.3
E 10.63
F 10.96
Stall and Motion Detection
Motion detection is based on the Back Electromotive
Force (BEMF or back emf) generated into the running
motor. When the motor is blocked, e.g. when it hits the
end−position, the velocity and as a result also the generated
back emf, is disturbed. The NCV70514 measures the back
emf during the current zero crossing phase and makes it
available in the SPI status register 4. The back emf voltage
is measured several times in each PWM cycle during zero
crossing phase. Samples taken during PWM ON phase of the
switches in the second coil are discarded not to add noise to
measurement (see Figure 14). Results are then converted
into a 5−bits word <Bemf[4:0]> with the following formula:
BEMF_code(dec) +
V_MOT_XorY_diff(V) @ Gain @
ǒ
5
4
Ǔ
@
2
5
2.41
When the result is ready, it is indicated by <BemfRes> bit
in status register.
When using normal mode of back emf measurement
(<EnhBemfEn> = 0), last sample before end of current zero
crossing phase becomes available in <Bemf[4:0]> register
(see the red circle on Figure 14).
When the enhanced back emf measurement mode is set by
<EnhBemfEn> bit, all non discarded results are
continuously available in <Bemf[4:0]> register (see red and
all black circles on Figure 14). This allows microcontroller
