NCV70514MW003AR2G Datasheet NCV70514MW003AR2G, NCV70514MW003G, NV705143R1DBGEVB | P25-P27

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Table 17. SPI CONTROL REGISTERS (CR)

4−bit

Address

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Default

after Reset

01h or 11h

(CR1)

DIRP RHBP NXTP MOTEN StThr3 StThr2 StThr1 StThr0 0000 0000

02h or 12h

(CR2)

Ihold3 Ihold2 Ihold1 Ihold0 Irun3 Irun2 Irun1 Irun0 0000 0000

03h or 13h

(CR3)

EnhBemf En DIAGEN EMC1 EMC0 SLP SM2 SM1 SM0 0010 0000

04h (CR4) StTo7 StTo6 StTo5 StTo4 StTo3 StTo2 StTo1 StTo0 0001 0000

05h or 15h

(CR5)

SpThr7 SpThr6 SpThr5 SpThr4 SpThr3 SpThr2 SpThr1 SpThr0 0000 0000

06h or 16h

(CR6)

UV1Thr3 UV1Thr2 UV1Thr1 UV1Thr0 UV2Thr3 UV2Thr2 UV2Thr1 UV2Thr0 0000 0000

07h or 17h

(CR7)

AD4 BemfGain Bemf

ResIntEn

UV1IntEn UV2IntEn UV2MIntEn UV3IntEn UV3MIntEn 0000 0000

14h (CR4A) NotUsed NotUsed NotUsed Iboost OpenDet1 OpenDet0 OpenDis OpenHiZ 0000 0100

NCV70514 responds on every incoming byte by shifting out the data stored on the last address sent via the bus. After POR

the initial address is unknown, so the first data shifted out are undefined.

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Table 18. BIT DEFINITION

Symbol MAP position Description

DIRP Bit 7 – ADDR_0x01 or 0x11 (CR1) Polarity of DIR pin, which controls direction status; DIRP = 1 inverts the

logic polarity of the DIR pin)

RHBP Bit 6 – ADDR_0x01 or 0x11 (CR1) Polarity of RHB pin, which controls RUN/HOLD status; RHBP = 1 inverts

logic polarity of the RHB pin (Hold = NOT(RHB XOR <RHBP>))

NXTP Bit 5 – ADDR_0x01 or 0x11 (CR1) Push button pin, generating next step in position table

MOTEN Bit 4 – ADDR_0x01 or 0x11 (CR1) Enables the H−bridges (motor activated in RUN or HOLD mode)

StThr[3:0] Bits [3:0] – ADDR_0x01 or 0x11 (CR1) Threshold level for stall detection, when “0”, stall detection is disabled

Ihold[3:0] Bits [7:4] – ADDR_0x02 or 0x12 (CR2) Current amplitude in HOLD mode

Irun[3:0] Bits [3:0] – ADDR_0x02 or 0x12 (CR2) Current amplitude in RUN mode

EnhBemfEn Bit 7 – ADDR_0x03 or 0x13 (CR3) Enhanced BEMF measurement functionality is activated when bit is set

DIAGEN Bit 6 – ADDR_0x03 or 0x13 (CR3) Enables automatic diagnostic at rising edge of <MOTEN> bit

EMC[1:0] Bits [5:4] – ADDR_0x03 or 0x13 (CR3) Voltage slope defining bits for motor driver switching

SLP Bit 3 – ADDR_0x03 or 0x13 (CR3) Places device in sleep mode with low current consumption (when 1)

SM[2:0] Bits [2:0] – ADDR_0x03 or 0x13 (CR3) Step mode selection

StTo[7:0] Bits [7:0] – ADDR_0x04 (CR4) Max difference between two successive full step next pulse periods (time-

out), after this time the BEMF sample is taken to verify stall

SpThr[7:0] Bits [7:0] – ADDR_0x05 or 0x15 (CR5) Speed threshold register, BEMF measurement and stall detection is acti-

vated when Speed register value is less than or equal to <SpThr> value

UV1Thr[3:0] Bits [7:4] – ADDR_0x06 or 0x16 (CR6) Setting of under voltage level UV1. See chapter UV detection

UV2Thr[3:0] Bits [3:0] – ADDR_0x06 or 0x16 (CR6) Setting of under voltage level UV2. See chapter UV detection

AD4 Bit 7 – ADDR_0x07 or 0x17 (CR7) Address selection bit, alternating register ”Banks”. When AD = 1, all

addresses will be interpreted with a ”1” in the first nibble (allowing to

access registers CR4A, SR7A, SR8A). When AD = 0, all addresses will be

interpreted with a ”0” in the first nibble (allowing to access registers CR4,

SR7, SR8).

BemfGain Bit 6 – ADDR_0x07 or 0x17 (CR7) Gain of BEMF measurement channel − “0”: gain 0.5, “1”: gain 0.25

BemfResIntEn Bit 5 – ADDR_0x07 or 0x17 (CR7) BEMF result interrupt enable

UV1IntEn Bit 4 – ADDR_0x07 or 0x17 (CR7) Under voltage 1 detection interrupt enable

UV2IntEn Bit 3 – ADDR_0x07 or 0x17 (CR7) Under voltage 2 detection interrupt enable

UV2MIntEn Bit 2 – ADDR_0x07 or 0x17 (CR7) Under voltage 2 detection and Motion interrupt enable

UV3IntEn Bit 1 – ADDR_0x07 or 0x17 (CR7) Under voltage 3 detection interrupt enable

UV3MIntEn Bit 0 – ADDR_0x07 or 0x17 (CR7) Under voltage 3 detection and Motion interrupt enable

Iboost Bit 4 – ADDR_0x14 (CR4A) Motor current boost function activation and status

OpenDet[1:0] Bits [3:2] – ADDR_0x14 (CR4A)

Open Coil detection time setting bits (see Table 7 − AC PARAMETERS)

OpenDis Bit 1 – ADDR_0x14 (CR4A) When bit is set, Open Coil detection status is flagged, but drivers control

remain active for both coils, <OpenDis> bit setting has higher priority than

<OpenHiZ> bit

OpenHiZ Bit 0 – ADDR_0x04 (CR4A) When bit is set, during Open Coil detection both drivers are deactivated

(MOTEN=0)

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SPI Status Registers (SR)

All SPI status registers have Read Only Access, with the odd parity on Bit7. Parity bit makes the numbers of 1 in the byte odd.

Table 19. SPI STATUS REGISTERS (SR)

4−bit

Address

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Comment

Default

after

Reset

08h or 18h

(SR1)

PAR SPI,L SHORT,R* OPEN,R* TSD,L TW,R STALL,L HR,L Errors 0xx 0001

09h or 19h

(SR2)

PAR ORErr, R BemfRes UV1,L UV2,L UV2M,L UV3,L UV3M,L INTst 101 1010

0Ah or 1Ah

(SR3)

PAR MSP6,R MSP5,R MSP4,R MSP3,R MSP2,R MSP1,R MSP0,R Micro−step

position

001 0000

0Bh or 1Bh

(SR4)

PAR BemfCoil, R Bemfs, R Bemf4, R Bemf3, R Bemf2, R Bemf1, R Bemf0, R Bemf x00 0000

0Ch or 1Ch

(SR5)

Sp7,R Sp6,R Sp5,R Sp4,R Sp3 ,R Sp2,R Sp1,R Sp0,R Speed 1111 1111

0Dh or 1Dh

(SR6)

PAR Sl6,L Sl5,L Sl4,L Sl3,L Sl2,L Sl1,L Sl0,L StepLoss 000 0000

0Eh (SR7) PAR T/BX,R SignX,R PWMX4,R PWMX3,R PWMX2,R PWMX1,R PWMX0,R PWMX 000 0000

0Fh (SR8) PAR T/BY,R SignY,R PWMY4,R PWMY3,R PWMY2,R PWMY1,R PWMY0,R PWMY 000 0000

1Eh (SR7A) PAR OPENX,L STEP0pin,R STEP1pin,R SHRTXPB,L SHRTXNB,L SHRTXPT,L SHRTXNT,L Input pins

& ShortsX

xxx 0000

1Fh (SR8A) PAR OPENY,L RHBpin,R DIRpin, R SHRTYPB,L SHRTYNB,L SHRTYPT,L SHRTYNT,L Input pins

& ShortsY

xxx 0000

Flags have “,L” for latched information or “,R” for real time information. All latched flags are “cleared upon read”.

X = value after reset is defined during reset phase (diagnostics)

R* = real time read out of values of other latches. Reading out this R* value does not reset the bit, and does not reset the values of the

latches this bit reads out.

Table 20. BIT DEFINITION

Symbol MAP Position Description

PAR Bit 7 – ADDR_0x08 or 0x18 (SR1) Parity bit for SR1

SPI Bit 6 – ADDR_0x08 or 0x18 (SR1) SPI error: no multiple of 16 rising clock edges between falling and rising

edge of CSB line

SHORT Bit 5 – ADDR_0x08 or 0x18 (SR1) An over current detected (common: set if at least one of the SHORTij indi-

vidual bits is set)

OPEN Bit 4 – ADDR_0x08 or 0x18 (SR1) Open Coil X or Y detected (common: set if at least one of the two specific

X/Y open coil bits is set)

TSD Bit 3 – ADDR_0x08 or 0x18 (SR1) Thermal shutdown

TW Bit 2 – ADDR_0x08 or 0x18 (SR1) Thermal warning

STALL Bit 1 – ADDR_0x08 or 0x18 (SR1) Stall detected by the internal algorithm

HR Bit 0 – ADDR_0x08 or 0x18 (SR1) Hard reset flag: 1 indicates a hard reset has occurred

PAR Bit 7 – ADDR_0x09 or 0x19 (SR2) Parity bit for SR2

ORErr Bit 6 – ADDR_0x09 or 0x19 (SR2) Logic OR of all bits of SR1 (Error bits)

BemfRes Bit 5 – ADDR_0x09 or 0x19 (SR2) BEMF result ready at <Bemf> register

UV1 Bit 4 – ADDR_0x09 or 0x19 (SR2) Under voltage 1 detection

UV2 Bit 3 – ADDR_0x09 or 0x19 (SR2) Under voltage 2 detection

UV2M Bit 2 – ADDR_0x09 or 0x19 (SR2) Under voltage 2 detection and NXT pulse arrive during UV2 state (Motion)

UV3 Bit 1 – ADDR_0x09 or 0x19 (SR2) Under voltage 3 detection

UV3M Bit 0 – ADDR_0x09 or 0x19 (SR2) Under voltage 3 detection and NXT pulse arrive during UV3 state (Motion)

PAR Bit 7 – ADDR_0x0A or 0x1A (SR3) Parity bit for SR3

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P31

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Motor / Motion / Ignition Controllers & Drivers BIPOLAR STEPPER MOTOR GRE

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