IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
2006 Integrated Device Technology, Inc.
DSC-6242/4
1 November 14, 2012
WAN PLL WITH SINGLE
REFERENCE INPUT IDT82V3001A
DESCRIPTION
The IDT82V3001A is a WAN PLL with single reference input. It
contains a Digital Phase-Locked Loop (DPLL), which generates ST-BUS
clocks and framing signals that are phase locked to a 2.048 MHz, 1.544
MHz or 8 kHz input reference.
The IDT82V3001A provides eight types of clock signals (C1.5o, C3o,
C6o, C2o, C4o, C8o, C16o, C32o) and six types of framing signals (F0o,
F8o, F16o, F32o, RSP, TSP) for the multitrunk T1 and E1 primary rate
transmission links.
The IDT82V3001A is compliant with AT&T TR62411, Telcordia GR-
1244-CORE Stratum 4 Enhanced and Stratum 4, ETSI ETS 300 011. It
FEATURES
Supports AT&T TR62411 and Telcordia GR-1244-CORE Stra-
tum 4 Enhanced and Stratum 4 timing for DS1 interfaces
Supports ETSI ETS 300 011, TBR 4, TBR 12 and TBR 13 tim-
ingfor E1 interface
Selectable input reference signal: 8 kHz, 1.544 MHz or 2.048
MHz
Provides eight types of clock signals: C1.5o, C3o, C2o, C4o,
C6o, C8o, C16o and C32o
Provides six types of 8 kHz framing pulses: F0o, F8o, F16o,
F32o, RSP and TSP
Holdover frequency accuracy of 0.025 ppm
Phase slope of 5 ns/125 µs
Attenuates wander from 2.1 Hz
Fast Lock mode
Provides Time Interval Error (TIE) correction
MTIE of 600 ns
JTAG boundary scan
Holdover status indication
Freerun status indication
Normal status indication
Lock status indication
3.3 V operation with 5 V tolerant I/O
Package available: 56-pin SSOP (Green option available)
meets the jitter/wander tolerance, jitter/wander transfer, intrinsic jitter/
wander, frequency accuracy, capture range, phase change slope,
holdover frequency accuracy and MTIE (Maximum Time Interval Error)
requirements for these specifications.
The IDT82V3001A can be used in synchronization and timing control
for T1 and E1 systems, or used as ST-BUS clock and frame pulse
sources. It can also be used in access switch, access routers, ATM edge
switches, wireless base station controllers, or IADs (Integrated Access
Devices), PBXs and line cards.
FUNCTIONAL BLOCK DIAGRAM 2 November 14, 2012
IDT82V3001A WAN PLL WITH SINGLE REFERENCE INPUT
FUNCTIONAL BLOCK DIAGRAM
Figure - 1 Block Diagram
OSC
TIE Control
Block
DPLL
Input Frequency
Selection
State Control Circuit
OSCi
OSCo
TCLR
V
DDA
V
SS
V
SS
C32o
C16o
C8o
C4o
C2o
C3o
C6o
F0o
F8o
RSP
TSP
F_sel0F_sel1FREERUNNORMAL HOLDOVER
TDO
TDI
Fref
FLOCK
Invalid Input
Signal
Detection
F16o
C1.5o
JTAG
LOCK
MODE_sel0MODE_sel1TIE_en
TMS
TRST
TCK
V
DDA
V
SS
V
DDD
V
DDD
V
SS
RST
F32o
Virtual
Reference
Feedback
Signal
V
DDD
V
SS
Table Of Contents 3 November 14, 2012
TABLE OF CONTENTS
1 IDT82V3001A PIN CONFIGURATION...........................................................................................................................6
2 PIN DESCRIPTION........................................................................................................................................................7
3 FUNCTIONAL DESCRIPTION.....................................................................................................................................10
3.1 State Control Circuit.............................................................................................................................................10
3.1.1 Normal Mode............................................................................................................................................11
3.1.2 Fast Lock Mode........................................................................................................................................11
3.1.3 Holdover Mode .........................................................................................................................................11
3.1.4 Freerun Mode...........................................................................................................................................12
3.2 Frequency Select Circuit......................................................................................................................................12
3.3 Invalid Input Signal Detection..............................................................................................................................12
3.4 TIE Control Block...........................................................................................................
......................................12
3.5 DPLL Block..........................................................................................................................................................14
3.5.1 Phase Detector (PHD)..............................................................................................................................14
3.5.2 Limiter.......................................................................................................................................................14
3.5.3 Loop Filter.................................................................................................................................................14
3.5.4 Fraction Block...........................................................................................................................................15
3.5.5 Digital Control Oscillator (DCO)................................................................................................................15
3.5.6 Lock Indicator ...........................................................................................................................................15
3.5.7 Output Interface........................................................................................................................................15
3.6 OSC.....................................................................................................................................................................15
3.6.1 Clock Oscillator.........................................................................................................................................15
3.7 JTAG....................................................................................................................................................................15
3.8 Reset Circuit........................................................................................................................................................15
3.9 Power Supply Filtering Techniques.....................................................................................................................16
4 MEASURES OF PERFORMANCE..............................................................................................................................17
4.1 Intrinsic Jitter........................................................................................................................................................17
4.2 Jitter Tolerance....................................................................................................................................................17
4.3 Jitter Transfer.......................................................................................................................................................17
4.4 Frequency Accuracy............................................................................................................................................17
4.5 Holdover Accuracy...............................................................................................................................................17
4.6 Capture Range ....................................................................................................................................................17
4.7 Lock Range..................................................................................................................
........................................17
4.8 Phase Slope ........................................................................................................................................................17
4.9 Time Interval Error (TIE)......................................................................................................................................17
4.10 Maximum Time Interval Error (MTIE) ..................................................................................................................17
4.11 Phase Continuity..................................................................................................................................................17
4.12 Phase Lock Time.................................................................................................................................................18
5 TEST SPECIFICATIONS .............................................................................................................................................19
5.1 AC Electrical Characteristics**.............................................................................................................................20
6 TIMING CHARACTERISTICS......................................................................................................................................24
7 ORDERING INFORMATION........................................................................................................................................28

82V3001APVG8

Mfr. #:
Manufacturer:
IDT
Description:
Clock Generators & Support Products 3.3V T1/E1 Stratum 4 /4E single ref WAN
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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