TIMING CHARACTERISTICS 25 November 14, 2012
IDT82V3001A WAN PLL WITH SINGLE REFERENCE INPUT
Figure - 12 Input to Output Timing (Normal Mode)
t
C2W
C2o pulse width high or low 244 ns
t
C4W
C4o pulse width high or low 122 ns
t
C8W
C8o pulse width high or low 61 ns
t
C16WL
C16o pulse width high or low 30.5 ns
t
C32WH
C32o pulse width high 14.4 ns
t
TSPW
TSP pulse width high 486 ns
t
RSPW
RSP pulse width high 490 ns
t
F0WL
F0o pulse width low 243 ns
t
F8WH
F8o pulse width high 123.6 ns
t
F16WL
F16o pulse width low 60.9 ns
t
0RF
Output clock and frame pulse rise or fall time 3 ns
t
S
Input Controls Setup Time 100 ns
t
H
Input Controls Hold Time 100 ns
t
F16D
F8o to F16o delay 27.1 30.1 33.1 ns
t
F32D
F8o to F32o delay 12 15.8 19 ns
t
F32S
F32o setup to C32o falling 11 ns
t
F32H
F32o hold to C32o falling 11 ns
t
F32WL
F32o pulse width low 30.6 ns
Table - 18 Input / Output Timing (Continued)
Parameter Description Min Typ Max Units Test Conditions
t
R8D
t
RW
t
R15D
t
RW
t
RW
t
R2D
V
T
V
T
V
T
V
T
Fref
8 kHz
Fref
1.544 MHz
Fref
2.048 MHz
F8o
