FUNCTIONAL DESCRIPTION 12 November 14, 2012
IDT82V3001A WAN PLL WITH SINGLE REFERENCE INPUT
3.1.4 FREERUN MODE
Freerun Mode is typically used when a master clock source is
required, or a system is just powered up and the network
synchronization has not been achieved.
In Freerun Mode, the IDT82V3001A provides timing and
synchronization signals which are based on the master clock frequency
(OSCi) only and not synchronized to the input reference signal.
The accuracy of the output clock is equal to the accuracy of the
master clock (OSCi). So if a ±32 ppm output clock is required, the
master clock must also be ±32 ppm. Refer to "OSC" section for more
information.
The FREERUN pin will go high whenever the IDT82V3001A works in
Freerun Mode.
3.2 FREQUENCY SELECT CIRCUIT
The IDT82V3001A accepts one reference input signal, Fref, and
operates on its falling edge. The input reference can be 8 kHz, 1.544
MHz or 2.048 MHz. As shown in Table - 3, the F_sel1 and F_sel0 pins
determine which of the three frequencies is selected. Every time the
frequency is changed, the device must be reset to make the change
effective.
3.3 INVALID INPUT SIGNAL DETECTION
This circuit monitors the input reference signal into the
IDT82V3001A. The IDT82V3001A will automatically enter Holdover
Mode (Auto-Holdover) if the incoming reference signal is out of the
capture range (See Table - 7), including a complete loss of input
reference, or a large frequency shift in the input reference. When the
input reference returns to normal, the DPLL will return to Normal Mode.
In Holdover Mode, the output signal of the IDT82V3001A is based on
the output signal 30 ms to 60 ms prior to entering Holdover Mode. The
amount of phase drift in Holdover Mode is negligible because Holdover
Mode is very accurate (e.g., 0.025 ppm). Consequently, the phase delay
between the input and output after switching back to Normal Mode is
preserved.
3.4 TIE CONTROL BLOCK
If the current reference is badly damaged or lost, it is necessary to
use the reference generated by the storage techniques instead. But
when switching the operation mode, a step change in phase on the input
reference will occur. And a step change in phase at the input of the
DPLL would lead to unacceptable phase changes in the output signals.
The TIE control block, when enabled, prevents a step change in phase
on the input reference signals from causing a step change in phase at
the output of the DPLL block. Figure - 5 shows the TIE Control Block
diagram.
Figure - 5 TIE Control Circuit Diagram
The TIE Control Block will work under the control of the Step
Generation circuit when it is enabled manually or automatically (by the
TIE_en pin or TIE auto-enable logic generated by the State Control
Circuit).
The input reference signal is compared with the feedback signal
(current output feedback from the Frequency Select Circuit) by the
Measure Circuit. The phase difference between the input reference and
the feedback signal is sent to the Storage Circuit for TIE correction. The
Trigger Circuit generates a virtual reference with the phase corrected to
the same position as the previous reference according to the value
stored in the Storage Circuit. With this TIE correction mechanism, the
reference is switched without generating a step change in phase.
Figure - 6 shows the phase transient that would result if a state
switch is performed with the TIE Control Block enabled.
Table - 3 Input Reference Frequency Selection
F_sel1 F_sel0 Input Frequency
00 Reserved
01 8 kHz
1 0 1.544 MHz
1 1 2.048 MHz
Step Generation
TIE_en
Measure
Circuit
Storage
Circuit
Trigger Circuit
Feedback
signal
TCLR
Fref
Virtual
Reference
Signal
