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82V3001APVG8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
TEST SPECIFICATIONS 22 November 14, 2012
IDT82V3001A WAN PLL WITH SINGLE REFERENCE INPUT
Table - 13 2.048 MHz Input to 2.048 MHz Output Jitter Transfer
Description Min Typ Max Units Test Conditions / Notes*
Jitter at output for 1 Hz@3.00 UIpp input 2.5 UIpp 1, 6, 7-12, 19-20, 22, 28, 33
Jitter at output for 1 Hz@3.00 UIpp input with 40 Hz to 100 Hz filter 0.07 UIpp 1, 6, 7-12, 19-20, 22, 28, 34
Jitter at output for 3 Hz@2.33 UIpp input 1.4 UIpp 1, 6, 7-12, 19-20, 22, 28, 33
Jitter at output for 3 Hz@2.33 UIpp input with 40 Hz to 100 Hz filter 0.10 UIpp 1, 6, 7-12, 19-20, 22, 28, 34
Jitter at output for 5 Hz@2.07 UIpp input 0.90 UIpp 1, 6, 7-12, 19-20, 22, 28, 33
Jitter at output for 5 Hz@2.07 UIpp input with 40 Hz to 100 Hz filter 0.10 UIpp 1, 6, 7-12, 19-20, 22, 28, 34
Jitter at output for 10 Hz@1.76 UIpp input 0.40 UIpp 1, 6, 7-12, 19-20, 22, 28, 33
Jitter at output for 10 Hz@1.76 UIpp input with 40 Hz to 100 Hz filter 0.10 UIpp 1, 6, 7-12, 19-20, 22, 28, 34
Jitter at output for 100 Hz@1.50 UIpp input 0.06 UIpp 1, 6, 7-12, 19-20, 22, 28, 33
Jitter at output for 100 Hz@1.50 UIpp input with 40 Hz to 100 Hz filter 0.05 UIpp 1, 6, 7-12, 19-20, 22, 28, 34
Jitter at output for 2400 Hz@1.50 UIpp input 0.04 UIpp 1, 6, 7-12, 19-20, 22, 28, 33
Jitter at output for 2400 Hz@1.50 UIpp input with 40 Hz to 100 Hz filter 0.03 UIpp 1, 6, 7-12, 19-20, 22, 28, 34
Jitter at output for 100 kHz@0.20 UIpp input 0.04 UIpp 1, 6, 7-12, 19-20, 22, 28, 33
Jitter at output for 100 kHz@0.20 UIpp input with 40 Hz to 100 Hz filter 0.02 UIpp 1, 6, 7-12, 19-20, 22, 28
Table - 14 8 kHz Input Jitter Tolerance
Description Min Typ Max Units Test Conditions / Notes*
Jitter tolerance for 1 Hz input 0.80 UIpp 1, 4, 7-12, 19-20, 22-24, 26
Jitter tolerance for 5 Hz input 0.70 UIpp 1, 4, 7-12, 19-20, 22-24, 26
Jitter tolerance for 20 Hz input 0.60 UIpp 1, 4, 7-12, 19-20, 22-24, 26
Jitter tolerance for 300 Hz input 0.16 UIpp 1, 4, 7-12, 19-20, 22-24, 26
Jitter tolerance for 400 Hz input 0.14 UIpp 1, 4, 7-12, 19-20, 22-24, 26
Jitter tolerance for 700 Hz input 0.07 UIpp 1, 4, 7-12, 19-20, 22-24, 26
Jitter tolerance for 2400 Hz input 0.02 UIpp 1, 4, 7-12, 19-20, 22-24, 26
Jitter tolerance for 3600 Hz input 0.01 UIpp 1, 4, 7-12, 19-20, 22-24, 26
Table - 15 1.544 MHz Input Jitter Tolerance
Description Min Typ Max Units Test Conditions / Notes*
Jitter tolerance for 1 Hz input 150 UIpp 1, 5, 7-12, 19-20, 22-24, 27
Jitter tolerance for 5 Hz input 140 UIpp 1, 5, 7-12, 19-20, 22-24, 27
Jitter tolerance for 20 Hz input 130 UIpp 1, 5, 7-12, 19-20, 22-24, 27
Jitter tolerance for 300 Hz input 38 UIpp 1, 5, 7-12, 19-20, 22-24, 27
Jitter tolerance for 400 Hz input 25 UIpp 1, 5, 7-12, 19-20, 22-24, 27
Jitter tolerance for 700 Hz input 15 UIpp 1, 5, 7-12, 19-20, 22-24, 27
Jitter tolerance for 2400 Hz input 5 UIpp 1, 5, 7-12, 19-20, 22-24, 27
Jitter tolerance for 10 kHz input 1.2 UIpp 1, 5, 7-12, 19-20, 22-24, 27
Jitter tolerance for 40 kHz input 0.5 UIpp 1, 5, 7-12, 19-20, 22-24, 27
TEST SPECIFICATIONS 23 November 14, 2012
IDT82V3001A WAN PLL WITH SINGLE REFERENCE INPUT
*Notes:
Voltages are with respect to ground (V
SS
) unless otherwise stated.
Supply voltage and operating temperature are as per Recommended Operating Conditions.
Timing parameters are as per AC Electrical Characteristics - Timing Parameter Measurement Voltage Levels
1. Normal Mode selected.
2. Holdover Mode selected.
3. Freerun Mode selected.
4. 8 kHz Frequency Mode selected.
5. 1.544 MHz Frequency Mode selected.
6. 2.048 MHz Frequency Mode selected.
7. Master clock input OSCi at 20 MHz ±0 ppm.
8. Master clock input OSCi at 20 MHz ±32 ppm.
9. Master clock input OSCi at 20 MHz ±100 ppm.
10. Selected reference input at 0 ppm.
11. Selected reference input at 32 ppm.
12. Selected reference input at 100 ppm.
13. For Freerun Mode of 0 ppm.
14. For Freerun Mode of 32 ppm.
15. For Freerun Mode of 100 ppm.
16. For capture range of 230 ppm.
17. For capture range of 198 ppm.
18. For capture range of 130 ppm.
19. 25 pF capacitive load.
20. OSCi Master Clock jitter is less than 2 nspp, or 0.04 UIpp where 1 UIpp = 1/20 MHz.
21. Jitter on reference input is obtained at slightly higher input jitter amplitudes.
22. Applied jitter is sinusoidal.
23. Minimum applied input jitter magnitude to regain synchronization.
24. Loss of synchronization is obtained at slightly higher input jitter amplitudes.
25. Within 10 ms of the state, reference or input change.
26. 1 UIpp = 125 µs for 8 kHz signals.
27. 1 UIpp = 648 ns for 1.544 MHz signals.
28. 1 UIpp = 488 ns for 2.048 MHz signals.
29. 1 UIpp = 323 ns for 3.088 MHz signals.
30. 1 UIpp = 244 ns for 4.096 MHz signals.
31. 1 UIpp = 122 ns for 8.192 MHz signals.
32. 1 UIpp = 61 ns for 16.484 MHz signals.
33. 1 UIpp = 30 ns for 32.968 MHz signals.
34. No filter.
35. 40 Hz to 100 kHz bandpass filter.
36. With respect to reference input signal frequency.
37. After chip reset or TIE reset.
38. Master clock duty 40% to 60%.
39. Prior to Holdover Mode, device as in Normal Mode and phase locked.
40. With input frequency offset of 100 ppm.
Table - 16 2.048 MHz Input Jitter Tolerance
Description Min Typ Max Units Test Conditions / Notes*
Jitter tolerance for 1 Hz input 150 UIpp 1, 6, 7-12, 19-20, 22-24, 28
Jitter tolerance for 5 Hz input 140 UIpp 1, 6, 7-12, 19-20, 22-24, 28
Jitter tolerance for 20 Hz input 130 UIpp 1, 6, 7-12, 19-20, 22-24, 28
Jitter tolerance for 300 Hz input 40 UIpp 1, 6, 7-12, 19-20, 22-24, 28
Jitter tolerance for 400 Hz input 33 UIpp 1, 6, 7-12, 19-20, 22-24, 28
Jitter tolerance for 700 Hz input 18 UIpp 1, 6, 7-12, 19-20, 22-24, 28
Jitter tolerance for 2400 Hz input 5.5 UIpp 1, 6, 7-12, 19-20, 22-24, 28
Jitter tolerance for 10 kHz input 1.3 UIpp 1, 6, 7-12, 19-20, 22-24, 28
Jitter tolerance for 100 kHz input 0.4 UIpp 1, 6, 7-12, 19-20, 22-24, 28
TIMING CHARACTERISTICS 24 November 14, 2012
IDT82V3001A WAN PLL WITH SINGLE REFERENCE INPUT
6 TIMING CHARACTERISTICS
Notes:
1. Voltages are with respect to ground (V
SS) unless otherwise stated.
2. Supply voltage and operating temperature are as per Recommended Operating Conditions.
3. Timing for input and output signals is based on the worst case result of the CMOS thresholds
Table - 17 Timing Parameter Measurement Voltage Levels
Parameter Description CMOS Units
V
T
Threshold Voltage
0.5V
DDD
V
V
HM
Rise and Fall Threshold Voltage High
0.7V
DDD
V
V
LM
Rise and Fall Threshold Voltage Low
0.3V
DDD
V
Table - 18 Input / Output Timing
Parameter Description Min Typ Max Units Test Conditions
t
RW
Reference input pulse width high or low 51 ns
t
IRF
Reference input rise or fall time 10 ns
t
R8D
8 kHz reference input to F8o delay 8 ns
t
R15D
1.544 MHz reference input to F8o delay 332 ns
t
R2D
2.048 MHz reference input to F8o delay 253 ns
t
F0D
F8o to F0o delay 118 121 124 ns
t
F16S
F16o setup to C16o falling 25 40 ns
t
F16H
F16o hold to C16o falling 25 40 ns
t
C15D
F8o to C1.5o delay -3 0 +3 ns
t
C3D
F8o to C3o delay -3 1.6 +3 ns
t
C6D
F8o to C6o delay -3 1.6 +3 ns
t
C2D
F8o to C2o -2 0 +2 ns
t
C4D
F8o to C4o -2 0 +2 ns
t
C8D
F8o to C8o delay -2 0 +2 ns
t
C16D
F8o to C16o delay -2 0 +2 ns
t
C32D
F8o to C32o delay -2 2 +2 ns
t
TSPD
F8o to TSP delay -3 0 +3 ns
t
RSPD
F8o to RSP delay -3 0 +3 ns
t
C15W
C1.5o pulse width high or low 323 ns
t
C3W
C3o pulse width high or low 161 ns
t
C6W
C6o pulse width high or low 82 ns
Timing Reference Points
t
IRF,
t
ORF
t
IRF,
t
ORF
V
HM
V
T
V
LM
ALL SIGNALS
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28

82V3001APVG8

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Buy 82V3001APVG8
Manufacturer:
IDT
Description:
Clock Generators & Support Products 3.3V T1/E1 Stratum 4 /4E single ref WAN
Lifecycle:
New from this manufacturer.
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