LTC4315
4
4315f
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
I
ACC(IN, Z)
Allowable Leakage Current in
the Open State
V
CC
= V
CC2
= 5V
l
±5 µA
V
READY(OL)
READY Output Low Voltage I
READY
= 3mA, V
CC
= 5V
l
0.4 V
I
READY(OH)
READY Off Leakage Current V
CC
= V
READY
= 5V
l
0.1 ±5 µA
Stuck Low Timeout Circuitry
t
TIMEOUT
Bus Stuck Low Timer SDAOUT or SCLOUT < 0.3 • V
MIN
(Note 5)
l
35 45 55 ms
V
FAULT(OL)
FAULT Output Low voltage I
FAULT
= 3mA
l
0.4 V
I
FAULT(OH)
FAULT Off Leakage Current V
CC
= V
FAULT
= 5V
l
0.1 ±5 µA
I
2
C Interface Timing
f
SCL(MAX)
I
2
C Frequency Max
l
400 kHz
t
PDHL
SCL, SDA Fall Delay V
CC
= V
CC2
= V
DD(BUS)
= 5V, C
BUS
= 100pF,
R
BUS
= 10k (Note 7)
130 250 ns
t
f
SCL, SDA Fall Times V
CC
= V
CC2
= V
DD(BUS)
= 5V, C
BUS
= 100pF,
R
BUS
= 10k (Note 7)
20 300 ns
t
IDLE
Bus Idle Time
l
55 95 175 µs
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into pins are positive and all voltages are referenced
to GND unless otherwise indicated.
Note 3: The LTC4315 can level translate bus voltages ranging from
2.25V to 5.5V. In special cases, it can also level translate down to 1.4V.
See the Applications Information section for more details.
Note 4: Test performed with SDA, SCL buffers active.
Note 5: V
MIN
= minimum of V
CC
and V
CC2
if V
CC2
> 2.25V, otherwise
V
MIN
= V
CC
.
Note 6: V
IL
is tested for the following (V
CC
, V
CC2
) combinations;
(2.9V, 5.5V), (5.5V, 2.25V), (3.3V, 3.3V) and (5V, 0V).
Note 7: Guaranteed by design and not tested.
Note 8: Measured in a special DC mode with V
SDA,SCL
= V
RTA(TH)
+ 1V.
The transient I
RTA
during rising edges, when ACC is LOW, will depend on
the bus loading condition and the slew rate of the bus. The LTC4315’s
internal slew rate control circuitry limits the maximum bus rise rate to
75V/µs by controlling the transient I
RTA
.
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. V
CC
= V
CC2
= 3.3V unless otherwise noted.
LTC4315
5
4315f
TYPICAL PERFORMANCE CHARACTERISTICS
Buffer DC I
OL
vs Temperature
t
PDHL
(50% to 50%) vs
Bus Capacitance
t
F
(70% to 30%) vs
Bus Capacitance
V
OS
vs I
BUS
Different Driven
Voltage Levels I
RTA
vs Temperature
I
CC
Enabled Current vs Supply
Voltage
I
CC
Disabled Current vs Supply
Voltage
I
CC2
Enabled Current vs Supply
Voltage
T
A
= 25°C, V
CC
= V
CC2
= 3.3V unless otherwise noted.
Bus Rise Time (40% to 70%) vs C
BUS
V
CC
(V)
2
I
CC
(mA)
9.0
8.0
7.0
8.5
7.5
6.5
6.0
435
4315 G01
63.52.5 4.5 5.5
V
SDAIN,SCLIN
= 0V
V
ENABLE
= 5.5V
V
CC
(V)
2
I
CC2
(mA)
0.4
0.2
0.3
0.1
435
4315 G03
63.52.5 4.5 5.5
V
SDAIN,SCLIN
= 0V
V
ENABLE
= 5.5V
C
BUS
(pF)
0
t
RISE
(ns)
75
5V
3.3V
100
600
4315 G09
50
25
200
400
800
V
CC
= V
CC2
= V
DD,BUS
ACC = 0V
V
CC
(V)
2
I
CC
(mA)
4.0
2.5
3.5
3.0
2.0
4352.5 4.53.5 5.5
4315 G02
6
V
SDAIN,SCLIN
= 0V
V
ENABLE
= 0V
TEMPERATURE (°C)
–50
I
RTA
(mA)
16
8
10
6
14
12
050
4315 G06
100–25
5V
25 75
V
CC
= V
CC2
= V
DD,BUS
V
SDA,SCL
t7
DD,BUS
C
BUS
= 400pF, R
BUS
= 10k
ACC = 0V
3.3V
TEMPERATURE (°C)
–50
I
OL
(mA)
12
5
6
11
10
4
8
9
7
050
4315 G04
100–25 25 75
V
SDA,SCL
= 0.6V
V
SDA,SCL
= 0.4V
I
BUS
(mA)
0
V
OS
(mV)
250
50
200
0
150
100
13
4315 G05
245
DRIVEN V
SDA,SCL
= 50mV
≥200mV
100mV
C
BUS
(pF)
0
t
F
(ns)
100
25
75
0
50
200 400
4315 G07
1000600 800
V
CC
= V
CC2
= V
DD,BUS
R
BUS
= 10k
5V
3.3V
C
BUS
(pF)
0
t
PDHL
(ns)
200
125
175
100
150
200 400
4315 G08
1000600 800
V
CC
= V
CC2
= V
DD,BUS
R
BUS
= 10k
5V
3.3V
LTC4315
6
4315f
PIN FUNCTIONS
ACC (Pin 5): Three-State Acceleration Strength Selector.
This pin controls the current strength of the rise time
accelerators on both the input and output sides. Rise
time accelerators (RTAs) are disabled if ACC is high,
in current source mode if ACC is open and in the slew
limited switch mode if ACC is low. See Table 1 in the
Applications Information section. Grounding V
CC2
selec-
tively disables the output side RTAs independent of the
ACC setting.
DISCEN (Pin 2): Enable Input to Disconnect Stuck Bus.
When this pin is high, stuck busses are automatically
disconnected after a timeout period of 45ms and FAULT
is pulled low. Up to sixteen clock pulses are subsequently
applied to SCLOUT. When DISCEN is low, stuck busses
are neither disconnected nor clocked but FAULT is pulled
low. Connect to GND if unused.
ENABLE (Pin 1): Connection Enable Input. When driven
low, the ENABLE pin isolates SDAIN and SCLIN from
SDAOUT and SCLOUT, asserts READY low, disables rise
time accelerators and inhibits automatic clock and stop bit
generation during a bus stuck low fault condition. When
driven high, the ENABLE pin connects SDAIN and SCLIN
to SDAOUT and SCLOUT after a stop bit or bus idle has
been detected on both busses. Driving ENABLE high also
enables automatic clock generation during a fault condition,
if DISCEN is tied high. During a fault condition, a rising
edge on the ENABLE pin forces a connection between
SDAIN and SDAOUT and SCLIN and SCLOUT. When using
the LTC4315 in a Hot Swap™ application with staggered
pins, connect a 10k resistor between ENABLE and GND
to ensure correct functionality. Connect to V
CC
if unused.
Exposed Pad (DE12 Package Only): Exposed pad may
be left open or connected to device GND.
FAUL T (Pin 8): Stuck Bus Fault Output. This open drain
N-channel MOSFET output pulls low if a simultaneous
high on SCLOUT and SDAOUT does not occur in 45ms. In
normal operation FAUL T is high. Connect a pull-up resis-
tor, typically 10k, from this pin to the bus pull-up supply.
Leave open or tie to GND if unused.
GND (Pin 6): Device Ground.
READY (Pin 7): Connection Ready Status Output. This
open drain N-channel MOSFET output pulls low when
the input and output sides are disconnected. READY is
pulled high when ENABLE is high and a connection has
been established between the input and output. Connect
a pull-up resistor, typically 10k, from this pin to the bus
pull-up supply. Leave open or tie to GND if unused.
SCLIN (Pin 4): Serial Bus 1 Clock Input/Output. Connect
this pin to the SCL line on the upstream bus. Connect an
external pull-up resistor or current source between this
pin and the bus supply. The bus supply must be ≥ V
CC
if rise time accelerators are enabled. Do not leave open.
SCLOUT (Pin 3): Serial Bus 2 Clock Input/Output. Con-
nect this pin to the SCL bus segment where stuck low
recovery is desired. Connect an external pull-up resistor
or current source between this pin and the bus supply.
The bus supply must be ≥ V
CC2
if rise time accelerators
are enabled. Do not leave open.
SDAIN (Pin 9): Serial Bus 1 Data Input/Output. Connect
this pin to the SDA line on the upstream bus. Connect an
external pull-up resistor or current source between this pin
and the bus supply. The bus supply must be ≥ V
CC
i f r i s e t i m e
accelerators are enabled. Do not leave open.
SDAOUT (Pin 10): Serial Bus 2 Data Input/Output. Con-
nect this pin to the SDA bus segment where stuck low
recovery is desired. Connect an external pull-up resistor
or current source between this pin and the bus supply.
The bus supply must be ≥ V
CC2
if rise time accelerators
are enabled. Do not leave open.
V
CC
(Pin 12): Power Supply Voltage. Power this pin from
a supply between 2.9V and 5.5V. Bypass with at least
0.01µF to GND.
V
CC2
(Pin 11): SDAOUT, SCLOUT Rise Time Accelerator
Power Supply Voltage. When powering V
CC2
, use a supply
voltage ranging from 2.25V to 5.5V and bypass with at
least 0.01µF to GND. Ou tpu t side r ise time acc elerators ar e
active if V
CC2
≥ 2.25V and ACC is low or open. Grounding
V
CC2
disables output side rise time accelerators indepen-
dent of the state of ACC.

LTC4315IMS#TRPBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Interface - Signal Buffers, Repeaters 2-Wire Bus Buffer with High Noise Margin w/ FAULT and SBDR Disable
Lifecycle:
New from this manufacturer.
Delivery:
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