19
LTC1609
1609fa
Output Data Format
The SB/BTC pin controls the format of the serial digital
output word. With the pin tied high the format is straight
binary. With the pin tied low the data format is two’s
complement. See Table 1c.
Board Layout, Power Supplies and Decoupling
Wire wrap boards are not recommended for high resolu-
tion or high speed A/D converters. To obtain the best
performance from the LTC1609, a printed circuit board is
required. Layout for the printed circuit board should
ensure the digital and analog signal lines are separated as
much as possible. In particular, care should be taken not
to run any digital track alongside an analog signal track or
underneath the ADC. The analog input should be screened
by AGND.
APPLICATIO S I FOR ATIO
WUUU
B15
01234567891011121314151617181920212223
• • •
• • •
R/C
BUSY
DCLK
DATA
OUT
B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3
DEVICE DATA #1 DEVICE DATA #2
B2 B1 B0
NULL
BIT
B14 B13 B12 B11 B10
1609 F14
B15
Figure 14. Data Output from Cascading Two (CS = Low, TAG (#2) = Low) LTC1609s Together
Pay particular attention to the design of the analog and
digital ground planes. Placing the bypass capacitor as
close as possible to the V
DIG
and V
ANA
pins, the REF pin
and reference buffer output is very important. Low imped-
ance common returns for these bypass capacitors are
essential to low noise operation of the ADC, and the foil
width for these tracks should be as wide as possible. Also,
since any potential difference in grounds between the
signal source and ADC appears as an error voltage in
series with the input signal, attention should be paid to
reducing the ground circuit impedance as much as pos-
sible. The digital output latches and the onboard sampling
clock have been placed on the digital ground plane. The
two ground planes are tied together at the power supply
ground connection.
A “postage stamp” (1.6in × 1.5in) evaluation board is
available and allows fast in-situ evaluation of the LTC1609.
See Figures 15a through 15d, inclusive.
