ADF4117BRUZ-RL Datasheet ADF4117BRUZ, ADF4116BRUZ, ADF4118BRUZ | P1-P3

RF PLL Frequency Synthesizers

ADF4116/ADF4117/ADF4118

Rev. D

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FEATURES

ADF4116: 550 MHz

ADF4117: 1.2 GHz

ADF4118: 3.0 GHz

2.7 V to 5.5 V power supply

Separate V

allows extended tuning voltage in 3 V systems

Y Grade: −40°C to +125°C

Dual-modulus prescaler

ADF4116: 8/9

ADF4117/ADF4118: 32/33

3-wire serial interface

Digital lock detect

Power-down mode

Fastlock mode

APPLICATIONS

Base stations for wireless radio

(GSM, PCS, DCS, CDMA, WCDMA)

Wireless handsets

(GSM, PCS, DCS, CDMA, WCDMA)

Wireless LANs

Communications test equipment

CATV equipment

GENERAL DESCRIPTION

The ADF411x family of frequency synthesizers can be used to

implement local oscillators (LO) in the upconversion and

downconversion sections of wireless receivers and transmitters.

They consist of a low noise digital phase frequency detector

(PFD), a precision charge pump, a programmable reference

divider, programmable A and B counters, and a dual-modulus

prescaler (P/P + 1). The A (5-bit) and B (13-bit) counters, in

conjunction with the dual-modulus prescaler (P/P + 1),

implement an N divider (N = BP + A). In addition, the 14-bit

reference counter (R counter) allows selectable REF

frequencies

at the PFD input. A complete phase-locked loop (PLL) can be

implemented if the synthesizer is used with an external loop

filter and voltage controlled oscillator (VCO).

All of the on-chip registers are controlled via a simple 3-wire

interface. The devices operate with a power supply ranging

from 2.7 V to 5.5 V and can be powered down when not in use.

FUNCTIONAL BLOCK DIAGRAM

REFERENCE

N = BP + A

FUNCTION

LATCH

PRESCALER

P/P + 1

14-BIT

R COUNTER

13-BIT

B COUNTER

5-BIT

A COUNTER

21-BIT

INPUT REGISTER

R COUNTER

LATCH

A, B COUNTER

LATCH

PHASE

FREQUENCY

DETECTOR

CHARGE

PUMP

M3 M2 M1

HIGH Z

MUX

MUXOUT

SWITCH

OUT

FROM

FUNCTION LATCH

DGNDAGNDCE

DATA

CLK

REF

CPGND

LOCK

DETECT

ADF4116/ADF4117/ADF4118

LOAD

00392-001

Figure 1.

ADF4116/ADF4117/ADF4118

Rev. D | Page 2 of 28

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

Circuit Description......................................................................... 12

Reference Input Section............................................................. 12

RF Input Stage............................................................................. 12

Prescaler (P/P + 1)...................................................................... 12

A Counter and B Counter ......................................................... 12

R Counter .................................................................................... 12

Phase Frequency Detector (PFD) and Charge Pump............ 13

MUXOUT and Lock Detect...................................................... 13

Input Shift Register..................................................................... 13

Latch Summaries........................................................................ 14

Latch Maps .................................................................................. 15

Function Latch ................................................................................ 19

Counter Reset ............................................................................. 19

Power-Down ............................................................................... 19

MUXOUT Control..................................................................... 19

Phase Detector Polarity ............................................................. 19

Charge Pump Three-State......................................................... 19

Fastlock Enable Bit..................................................................... 19

Fastlock Mode Bit....................................................................... 19

Timer Counter Control ............................................................. 19

Initialization Latch ..................................................................... 20

Device Programming After Initial Power-Up ........................ 20

Applications Information.............................................................. 21

Local Oscillator for the GSM Base Station Transmitter........ 21

Shutdown Circuit ....................................................................... 21

Direct Conversion Modulator .................................................. 21

Interfacing ................................................................................... 24

Outline Dimensions ....................................................................... 25

Ordering Guide .......................................................................... 25

REVISION HISTORY

4/07—Rev. C to Rev. D

Changes to REF

Characteristics Section..................................... 3

Changes to Table 4............................................................................ 7

Changes to Figure 35...................................................................... 22

Changes to Ordering Guide .......................................................... 25

11/05—Rev. B to Rev. C

Changes to Table 1............................................................................ 3

Changes to Table 2............................................................................ 5

Changes to Table 3............................................................................ 6

Changes to Table 4............................................................................ 7

Changed OSC 3B1-13M0 to FOX801BH-130............................ 21

Changes to Ordering Guide .......................................................... 25

9/04—Rev. A to Rev. B

Changes to Specifications.................................................................3

Changes to Ordering Guide.......................................................... 25

3/01—Rev. 0 to Rev. A

4/00—Rev. 0: Initial Version

ADF4116/ADF4117/ADF4118

Rev. D | Page 3 of 28

SPECIFICATIONS

= DV

= 3 V ± 10%, 5 V ± 10%; AV

≤ V

≤ 6.0 V; AGND = DGND = CPGND = 0 V; T

= T

MIN

to T

MAX

, unless otherwise

noted; dBm referred to 50 Ω.

Table 1.

Parameter B Version

Y Version

Unit Test Conditions/Comments

RF CHARACTERISTICS

RF Input Sensitivity −15 to 0 −10 to 0 dBm min to max AV

= 3 V

−10 to 0 −10 to 0 dBm min to max AV

= 5 V

RF Input Frequency

ADF4116 80 to 550 MHz min to max

See

Figure 26 for input circuit

45 to 550 MHz min to max

Input level = −8 dBm; for lower frequencies,

ensure slew rate (SR) > 36 V/μs

ADF4117 0.1 to 1.2 GHz min to max

ADF4118 0.1 to 3.0 0.1 to 3.0 GHz min to max Input level = −10 dBm

0.2 to 3.0 GHz min to max Input level = −15 dBm

Maximum Allowable Prescaler

Output Frequency

165

200

165

200

MHz max

, DV

= 3 V

, DV

= 5 V

REF

CHARACTERISTICS

Reference Input Frequency 5 to 100 5 to 100 MHz min to max For f < 5 MHz, ensure SR > 100 V/μs

Reference Input Sensitivity

4, 5

0.4 to AV

V p-p min to max AV

= 3.3 V, biased at AV

0.7 to AV

V p-p min to max For f ≥ 10 MHz, AV

= 5 V, biased at AV

REF

Input Capacitance 10 10 pF max

REF

Input Current ±100 ±100 μA max

PHASE DETECTOR FREQUENCY

55 55 MHz max

CHARGE PUMP

Sink/Source

High Value 1 1 mA typ

Low Value 250 250 μA typ

Absolute Accuracy 2.5 2.5 % typ

Three-State Leakage Current 3 25 nA max

1 16 nA typ

Sink and Source Current Matching 3 3 % typ 0.5 V ≤ V

≤ V

− 0.5

vs. V

2 2 % typ 0.5 V ≤ V

≤ V

− 0.5

vs. Temperature 2 2 % typ V

= V

LOGIC INPUTS

INH

, Input High Voltage 0.8 × DV

0.8 × DV

V min

INL

, Input Low Voltage 0.2 × DV

0.2 × DV

V max

INH

INL

, Input Current ±1 ± 1 μA max

, Input Capacitance 10 10 pF max

Reference Input Current ±100 ± 100 μA max

LOGIC OUTPUTS

, Output High Voltage DV

− 0.4 DV

− 0.4 V min I

= 500 μA

, Output Low Voltage 0.4 0.4 V max I

= 500 μA

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P28

ADF4117BRUZ-RL

Mfr. #:

Buy ADF4117BRUZ-RL

Manufacturer:

Analog Devices Inc.

Description:

Phase Locked Loops - PLL SGL Integer-N 1.2 GHz

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ADF4117BRUZ-RL

ADF4117BRUZ-RL

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