ADF4116/ADF4117/ADF4118
Rev. D | Page 12 of 28
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 25. SW1 and SW2
are normally closed switches; SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. This ensures that there is no loading of the REF
IN
pin
on power-down.
TO R COUNTER
REF
IN
100kΩ
NC
SW2
SW3
NO
NC
SW1
POWER-DOWN
CONTROL
BUFFER
00392-025
Figure 25. Reference Input Stage
RF INPUT STAGE
The RF input stage is shown in Figure 26. It is followed by a
2-stage limiting amplifier to generate the CML clock levels
needed for the prescaler.
AV
DD
AGND
500Ω500Ω
1.6V
BIAS
GENERATOR
RF
IN
A
RF
IN
B
00392-026
Figure 26. RF Input Stage
PRESCALER (P/P + 1)
The dual-modulus prescaler (P/P + 1), along with the A counter
and B counter, enables the large division ratio, N, to be realized
(N = PB + A). The dual-modulus prescaler takes the CML clock
from the RF input stage and divides it down to a manageable
frequency for the CMOS A counter and CMOS B counter. The
prescaler is programmable. It can be set in software to 8/9 for the
ADF4116 and to 32/33 for the ADF4117 and ADF4118. It is based
on a synchronous 4/5 core.
A COUNTER AND B COUNTER
The A CMOS counter and B CMOS counter combine with the
dual-modulus prescaler to allow a wide ranging division ratio in
the PLL feedback counter. The counters are specified to work
when the prescaler output is 200 MHz or less.
Pulse Swallow Function
The A counter and B counter, in conjunction with the dual-
modulus prescaler, make it possible to generate output
frequencies that are spaced only by the reference frequency
divided by R. The equation for the VCO frequency is as follows:
)
]
RfABPf
REFIN
VCO
/
where:
f
VCO
is the output frequency of external voltage controlled
oscillator (VCO).
P is the preset modulus of dual-modulus prescaler.
B is the preset divide ratio of binary 13-bit counter (3 to 8191).
A is the preset divide ratio of binary 5-bit swallow counter (0 to 31).
f
REFIN
is the output frequency of the external reference frequency
oscillator.
R is the preset divide ratio of binary 14-bit programmable
reference counter (1 to 16,383).
R COUNTER
The 14-bit R counter allows the input reference frequency to be
divided down to produce the input clock to the phase frequency
detector (PFD). Division ratios from 1 to 16,383 are allowed.
13-BIT
B COUNTER
5-BIT
A COUNTER
PRESCALER
P/P + 1
FROM RF
INPUT STAGE
MODULUS
CONTROL
N = BP + A
LOAD
LOAD
TO PFD
00392-027
Figure 27. A Counter and B Counter
