ADF4117BRUZ-RL Datasheet ADF4117BRUZ, ADF4116BRUZ, ADF4118BRUZ | P19-P21

ADF4116/ADF4117/ADF4118

Rev. D | Page 19 of 28

FUNCTION LATCH

With C2 and C1 set to 1 and 0, respectively, the on-chip

function latch is programmed.

Figure 33 shows the input data

format for programming the function latch.

COUNTER RESET

DB2 (F1) is the counter reset bit. When this bit is set to 1, the R

counter, A counter, and B counter are reset. For normal operation,

this bit should be set to 0. On power-up, the F1 bit needs to be

disabled, for the N counter to resume counting in “close”

alignment with the R counter. (The maximum error is one

prescaler cycle.)

POWER-DOWN

DB3 (PD1) and DB19 (PD2) on the ADF411x family provide

programmable power-down modes. They are enabled by the

CE pin.

When the CE pin is low, the device is immediately disabled

regardless of the states of PD2 and PD1.

In programmed asynchronous power-down, the device powers

down immediately after latching a 1 into the PD1 bit, with the

condition that PD2 is loaded with a 0.

In programmed synchronous power-down, the device power-

down is gated by the charge pump to prevent unwanted

frequency jumps. Once power-down is enabled by writing a 1

into the PD1 bit (on condition that a 1 is also loaded to PD2),

the device goes into power-down after the first successive

charge pump event.

When a power-down is activated (either synchronous or

asynchronous mode including CE pin-activated power-down),

the following events occur:

• All active dc current paths are removed.

• The R counter, N counter, and timeout counter are forced

to their load state conditions.

• The charge pump is forced into three-state mode.

• The digital clock detect circuitry is reset.

• The RF

input is debiased.

• The oscillator input buffer circuitry is disabled.

• The input register remains active and capable of loading

and latching data.

MUXOUT CONTROL

The on-chip multiplexer is controlled by DB6 (M3), DB5 (M2),

and DB4 (M1) on the ADF411x family.

Figure 33 shows the

truth table.

PHASE DETECTOR POLARITY

DB7 (F2) of the function latch sets the phase detector polarity.

When the VCO characteristics are positive, DB7 should be set

to 1. When they are negative, it should be set to 0.

CHARGE PUMP THREE-STATE

The DB8 (F3) bit puts the charge pump into three-state mode

when programmed to 1. It should be set to 0 for normal operation.

FASTLOCK ENABLE BIT

DB9 (F4) of the function latch is the fastlock enable bit. Fastlock

is enabled only when DB9 is set to 1.

FASTLOCK MODE BIT

DB11 (F6) of the function latch is the fastlock mode bit. When

fastlock is enabled, this bit determines which fastlock mode is

used. If the fastlock mode bit is 0, Fastlock Mode 1 is selected; if

the fastlock mode bit is 1, Fastlock Mode 2 is selected.

If fastlock is not enabled (DB9 = 0), DB11 (ADF4116)

determines the state of the FL

output. FL

state is the same as

that programmed to DB11.

Fastlock Mode 1

In the ADF411x family, the output level of FL

is programmed

to a low state, and the charge pump current is switched to the

high value (1 mA). FL

is used to switch a resistor in the loop

filter and to ensure stability while in fastlock by altering the

loop bandwidth.

The device enters fastlock by having a 1 written to the CP Gain

bit in the N register. The device exits fastlock by having a 0

written to the CP Gain bit in the N register.

Fastlock Mode 2

In the ADF411x family, the output level of FL

is programmed

to a low state, and the charge pump current is switched to the

high value (1 mA). FL

is used to switch a resistor in the loop

filter and to ensure stability while in fastlock by altering the

loop bandwidth.

The device enters fastlock by having a 1 written to the CP gain

bit in the N register. The device exits fastlock under the control

of the timer counter. After the timeout period determined by

the value in TC4 to TC1, the CP Gain bit in the N register is

automatically reset to 0, and the device reverts to normal mode

instead of fastlock.

TIMER COUNTER CONTROL

In the ADF411x family, the user has the option of switching

between two charge pump current values to speed up locking to

a new frequency.

When using the fastlock feature with the ADF411x family, the

following should be noted:

• The user must make sure that fastlock is enabled. Set DB9

to 1. The user must also choose which fastlock mode to use.

ADF4116/ADF4117/ADF4118

Rev. D | Page 20 of 28

• Fastlock Mode 2 uses the values in the timer counter to

determine the timeout period before reverting to normal

mode operation after fastlock. Fastlock Mode 2 is chosen

by setting DB11 to 1.

• The user must also decide how long to keep the high

current (1 mA) active before reverting to low current

(250 μA). This is controlled by the timer counter control

bits, DB14 to DB11 (TC4 to TC1), in the function latch.

The truth table is given in

Figure 33.

• To program a new output frequency, program the A counter

and B counter latch with new values for A and B. At the

same time, set the CP Gain bit to a 1, which sets the charge

pump to 1 mA for a period of time determined by TC4 to

TC1. When this time is up, the charge pump current

reverts to 250 μA. At the same time, the CP Gain bit in the

A counter and B counter latch is reset to 0 and is ready for

the next time that the user wants to change the frequency.

INITIALIZATION LATCH

When C2 and C1 are both set to 1, the initialization latch is

programmed. This is essentially the same as the function latch

that is programmed when C2, C1 = 1, 0.

However, when the initialization latch is programmed, an

additional internal reset pulse is applied to the R counter and

N counter. This pulse ensures that the N counter is at a load

point when the N counter data is latched and that the device

begins counting in close phase alignment.

If the latch is programmed for synchronous power-down (CE

pin is high; PD1 bit is high; PD2 bit is low), the internal pulse

also triggers this power-down. The prescaler reference and the

oscillator input buffer are unaffected by the internal reset pulse,

so close phase alignment is maintained when counting resumes.

When the first N counter data is latched after initialization, the

internal reset pulse is again activated. However, successive

N counter loads do not trigger the internal reset pulse.

DEVICE PROGRAMMING AFTER

INITIAL POWER-UP

After initial power-up, the device can be programmed by the

initialization latch method, the CE pin method, or the counter

reset method.

Initialization Latch Method

1. Apply V

2. Program the initialization latch (11 in 2 LSBs of input

word). Make sure that F1 bit is programmed to 0.

3. Do an R load (00 in 2 LSBs).

4. Do an N load (01 in 2 LSBs).

When the initialization latch is loaded, the following occurs:

• The function latch contents are loaded.

• An internal pulse resets the R, N, and timeout counters to

load state conditions and also three-states the charge pump.

Note that the prescaler band gap reference and the oscillator

input buffer are unaffected by the internal reset pulse, allowing

close phase alignment when counting resumes.

• Latching the first N counter data after the initialization

word activates the same internal reset pulse. Successive

N loads do not trigger the internal reset pulse unless there

is another initialization.

CE Pin Method

1. Apply V

2. Bring CE low to put the device into power-down. This is an

asynchronous power-down in that it happens immediately.

3. Program the function latch (10).

4. Program the R counter latch (00).

5. Program the N counter latch (01).

6. Bring CE high to take the device out of power-down.

The R counter and N counter resume counting in close alignment.

Note that after CE goes high, a duration of 1 μs may be required

for the prescaler band gap voltage and oscillator input buffer

bias to reach a steady state.

CE can be used to power up and power down the device to check

for channel activity. The input register does not need to be repro-

grammed each time the device is disabled and enabled, as long

as it is programmed at least once after V

is initially applied.

Counter Reset Method

1. Apply V

2. Do a function latch load (10 in 2 LSBs). As part of this,

load 1 to the F1 bit. This enables the counter reset.

3. Do an R counter load (00 in 2 LSBs).

4. Do an N counter load (01 in 2 LSBs).

5. Do a function latch load (10 in 2 LSBs). As part of this,

load 0 to the F1 bit. This disables the counter reset.

This sequence provides the same close alignment as the initiali-

zation method. It offers direct control over the internal reset.

Note that counter reset holds the counters at load point and

three-states the charge pump, but it does not trigger synchro-

nous power-down. The counter reset method requires an extra

function latch load compared to the initialization latch method.

ADF4116/ADF4117/ADF4118

Rev. D | Page 21 of 28

APPLICATIONS INFORMATION

LOCAL OSCILLATOR FOR THE

GSM BASE STATION TRANSMITTER

Figure 35 shows the ADF4117/ADF4118 being used with a

VCO to produce the LO for a GSM base station transmitter.

The reference input signal is applied to the circuit at F

REFIN

and,

in this case, is terminated in 50 Ω. A typical GSM system has a

13 MHz TCXO driving the reference input without a 50 Ω

termination. To have a channel spacing of 200 kHz (the GSM

standard), the reference input must be divided by 65, using the

on-chip reference divider of the ADF4117/ADF1118.

The charge pump output of the ADF4117/ADF1118 (Pin 2)

drives the loop filter. In calculating the loop filter component

values, a number of items need to be considered. In this example,

the loop filter was designed so that the overall phase margin for

the system is 45°. Other PLL system specifications include:

= 1 mA

= 12 MHz/V

Loop bandwidth = 20 kHz

REF

= 200 kHz

N = 4500

Extra reference spur attenuation = 10 dB

All of these specifications are needed and are used to produce

the loop filter component values shown in

Figure 36.

The loop filter output drives the VCO, which, in turn, is fed back

to the RF input of the PLL synthesizer; it also drives the RF

output terminal. A T-circuit configuration provides 50 Ω

matching between the VCO output, the RF output, and the

terminal of the synthesizer.

In a PLL system, it is important to know when the system is in

locked mode. In

Figure 35, this is accomplished by using the

MUXOUT signal from the synthesizer. The MUXOUT pin can

be programmed to monitor various internal signals in the

synthesizer. One of these is the LD or lock-detect signal.

SHUTDOWN CIRCUIT

The attached circuit in Figure 36 shows how to shut down both

the ADF411x family and the accompanying VCO. The ADG702

switch goes open-circuit when a Logic 1 is applied to the IN

input. The low cost switch is available in both SOT-23 and

MSOP packages.

DIRECT CONVERSION MODULATOR

In some applications, a direct conversion architecture can be

used in base station transmitters.

Figure 37 shows the

combination available from Analog Devices, Inc. to implement

this solution.

The circuit diagram shows the AD9761 being used with the

AD8346. The use of dual integrated DACs, such as the AD9761

with specified ±0.02 dB and ±0.004 dB gain and offset matching

characteristics, ensures minimum error contribution (over

temperature) from this portion of the signal chain.

The local oscillator is implemented by using the ADF4117/

ADF4118. In this case, the FOX801BH-130 provides the stable

13 MHz reference frequency. The system is designed for

200 kHz channel spacing and an output center frequency of

1960 MHz. The target application is a WCDMA base station

transmitter. Typical phase noise performance from this LO is

−85 dBc/Hz at a 1 kHz offset. The LO port of the AD8346 is

driven in single-ended fashion. LOIN is ac-coupled to ground

with the 100 pF capacitor, and LOIP is driven through the ac-

coupling capacitor from a 50 Ω source. An LO drive level between

−6 dBm and −12 dBm is required. The circuit in

Figure 37 gives a

typical level of −8 dBm.

The RF output is designed to drive a 50 Ω load, but it must be

ac-coupled as shown in

Figure 37. If the I and Q inputs are

driven in quadrature by 2 V p-p signals, the resulting output

power is approximately −10 dBm.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P28

ADF4117BRUZ-RL

Mfr. #:

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Manufacturer:

Analog Devices Inc.

Description:

Phase Locked Loops - PLL SGL Integer-N 1.2 GHz

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ADF4117BRUZ-RL

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